liuyic00

Pinned Repositories

riscv-spec-core
Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
Language:Scala5 1 04
CHA
Language:Scala0 0 00
chicala-soundness
Language:Scala0 1 01
chicala-stainless-try
Language:Scala01
chisel
Chisel: A Modern Hardware Design Language
Language:Scala0 0 00
chisel-playground
Language:Scala0 1 01
chisel-stinless-try
Language:Scala0 1 00
chiseltest
Repository for chisel3 testers2 open alpha
Language:Scala0 0 00
circt
Circuit IR Compilers and Tools
Language:C++0 0 00
mini-chisel-circuit
Language:Scala1 1 02

liuyic00's Repositories

liuyic00/mini-chisel-circuit
Language:Scala1 1 02
liuyic00/CHA
Language:Scala0 0 00
liuyic00/chicala-soundness
Language:Scala0 1 01
liuyic00/chicala-stainless-try
Language:Scala01
liuyic00/chisel
Chisel: A Modern Hardware Design Language
Language:Scala0 0 00
liuyic00/chisel-playground
Language:Scala0 1 01
liuyic00/chisel-stinless-try
Language:Scala0 1 00
liuyic00/chiseltest
Repository for chisel3 testers2 open alpha
Language:Scala0 0 00
liuyic00/circt
Circuit IR Compilers and Tools
Language:C++0 0 00
liuyic00/divider-stainless
Language:Scala
liuyic00/fakeZ3
Language:C++1 0
liuyic00/firrtl
Flexible Intermediate Representation for RTL
liuyic00/GCD
Language:Scala
liuyic00/leros
A Tiny Processor Core
Language:VHDL0 0
liuyic00/nutshell-fv
Formal verification on NutShell using riscv-spec-core
Language:Scala
liuyic00/pono
Next generation cosa.
Language:C++0 0
liuyic00/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
liuyic00/riscv-spec-core
Language:Scala
liuyic00/riscv-tests
Language:C0 01
liuyic00/riscv-tests-bin