Pinned Repositories
4NEC2_helical_gen
source code to generate .nec files for helical wire antennas
def
DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators
fpgaconvnet-hls
fpgaconvnet-model
Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
fpgaconvnet-optimiser
Optimiser for mapping convolutional neural network models to FPGA platforms.
fpgaconvnet-tutorial
A collection of tutorials for the fpgaConvNet framework.
fpgaconvnet-website
The work done at the Intelligent Digital Systems Lab at Imperial College London aims to address this demand with fpgaConvNet: a toolflow for designing Convolutional Neural Network (CNN) accelerators for FPGAs with state-of-the-art performance and efficiency.
pommel
Analysing power consumption of the memory subsystem for machine learning applications
samo
SAMO: Streaming Architecture Mapping Optimisation
satay
AlexMontgomerie's Repositories
AlexMontgomerie/samo
SAMO: Streaming Architecture Mapping Optimisation
AlexMontgomerie/fpgaconvnet-tutorial
A collection of tutorials for the fpgaConvNet framework.
AlexMontgomerie/fpgaconvnet-model
Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
AlexMontgomerie/fpgaconvnet-hls
AlexMontgomerie/satay
AlexMontgomerie/4NEC2_helical_gen
source code to generate .nec files for helical wire antennas
AlexMontgomerie/fpgaconvnet-optimiser
Optimiser for mapping convolutional neural network models to FPGA platforms.
AlexMontgomerie/def
DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators
AlexMontgomerie/pommel
Analysing power consumption of the memory subsystem for machine learning applications
AlexMontgomerie/fpgaconvnet-website
The work done at the Intelligent Digital Systems Lab at Imperial College London aims to address this demand with fpgaConvNet: a toolflow for designing Convolutional Neural Network (CNN) accelerators for FPGAs with state-of-the-art performance and efficiency.
AlexMontgomerie/huffman-chisel
A Chisel implementation of Huffman coding for a static code table
AlexMontgomerie/alexmontgomerie
AlexMontgomerie/rle-chisel
A Chisel implementation of single-value Run Length Encoding (RLE)
AlexMontgomerie/SMORE
Silent Mapping Order Randomisation Engine
AlexMontgomerie/axis_sink
AlexMontgomerie/BluespecIntroGuide
An introductory guide to Bluespec (BSV)
AlexMontgomerie/cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
AlexMontgomerie/deepLearning
AlexMontgomerie/DRAMPower
Fast and accurate DRAM power and energy estimation tool
AlexMontgomerie/DSAM
Scripts to obtain bit-level switching activity of CNNs. Requires Caffe.
AlexMontgomerie/ExtendedBitPlaneCompression
Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.
AlexMontgomerie/fccm-demo
AlexMontgomerie/finn
Dataflow compiler for QNN inference on FPGAs
AlexMontgomerie/graffitist
Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlow.
AlexMontgomerie/hpce-2018-cw1
AlexMontgomerie/ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
AlexMontgomerie/SCALE-Sim
AlexMontgomerie/teensy_loader_cli
Command line Teensy Loader
AlexMontgomerie/tiny
MLPerf™ Tiny is an ML benchmark suite for extremely low-power systems such as microcontrollers
AlexMontgomerie/yaml-cpp
A YAML parser and emitter in C++