chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++Apache-2.0
Issues
- 0
Wrong evaluation of unsized constant when used in operation with sized constant
#3979 opened by kamilrakoczy - 1
Fix compilation with newest gcc
#3976 opened by Kreijstal - 3
unable to elaborate cva6 (ariane)
#3972 opened by gadfort - 4
- 2
Getting ports in a module
#3973 opened by mysoreanoop - 1
Publish to package registries
#3845 opened by timkpaine - 2
Missing functional cover items in UHDM model
#3974 opened by dippmatt - 1
- 1
9 tests fail: Fatal Python error: PyEval_AcquireThread: the function must be called with the GIL held, but the GIL is released (the current Python thread state is NULL)
#3971 opened by yurivict - 1
surelog fails to create package files pkg/work/uvm_pkg.sv.slpp, pkg/work/uvm_pkg.sv.slpp, pkg/work/uvm_pkg.sv.slpp, pkg/work/uvm_pkg.sv.slpp
#3965 opened by yurivict - 6
- 0
Incorrect cmake installation instructions fail to install files into the stage directory
#3963 opened by yurivict - 3
Wrong Parameter calculation in the elaborated model
#3960 opened by Pietro4F - 12
Connect-by-name has no vpiHighConn
#3958 opened by pieter3d - 2
Can't determine struct member size in elaborated designs
#3959 opened by pieter3d - 1
Unresolved hierarchical reference when accessing elements packed array of packed struct
#3920 opened by hzeller - 8
- 3
fatal: Needed a single revision, Unable to find current origin/v1.74 revision in submodule path 'third_party/UHDM'
#3855 opened by alaindargelas - 6
Syntax error message cache is corrupted
#3852 opened by alaindargelas - 1
Better -y file filter
#3902 opened by alaindargelas - 9
Surelog Not Flagging Missing Time Delays, and Undefined Property References
#3814 opened by Divya2030 - 6
Identifying `reg` type in UHDM model
#3893 opened by hs-apotell - 2
Logging: "Creating log file" would be nicer without full-stop to allow for common terminal copy/paste workflow
#3849 opened by hzeller - 1
Logging: Superfluous newlines eat up vertical space and make logs hard to read
#3850 opened by hzeller - 3
Fix Windows CI build
#3873 opened by hs-apotell - 3
- 1
- 3
ExprEval returning io_del when returnTypespec is true
#3862 opened by hs-apotell - 3
- 1
Incorrect 128 bit function return val
#3848 opened by alaindargelas - 0
-defer, -link does not respect package ordering during compilation/elaboration (-link)
#3846 opened by alaindargelas - 2
configure looks for googlest when -DSURELOG_BUILD_TESTS=OFF and -DSURELOG_USE_HOST_GTEST=ON
#3826 opened by yurivict - 0
Non vendored build broken
#3831 opened by timkpaine - 2
- 10
Include a formatted text serializer to Surelog
#3818 opened by hs-apotell - 14
-defer , -link broken when -y used
#3812 opened by alaindargelas - 2
-y imported files should not generate UHDM tree if not used, nor generate errors.
#3819 opened by alaindargelas - 1
Potential typo in binding logic
#3823 opened by hs-apotell - 8
Parameter initialization with array assignment pattern containing `default` produces invalid elaborated UHDM
#3803 opened by mglb - 2
- 3
- 1
Procedural assertion after delay/event not allowed in SystemVerilog tests/SequenceInst/dut.sv
#3808 opened by Divya2030 - 1
surelog doesn't expand loop variables
#3771 opened by yurivict - 1
- 2
How does Surelog handle duplicate module names between sources and libraries?
#3790 opened by nmoroze - 2
Missing declarations of genvar in unnamed generate-for loops
#3789 opened by mglb - 7
- 7
surelog renaming wires with escape characters with #~@
#3776 opened by gadfort - 3
Comparison of `$bits` return value with scoped name of a parameter sometimes gives wrong result
#3772 opened by mglb - 2