uvm
There are 179 repositories under uvm topic.
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
maximecb/uvm
Fun, portable, minimalistic virtual machine.
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
taichi-ishitani/tvip-axi
AMBA AXI VIP
rggen/rggen
Code generation tool for control and status registers
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
troyguo/awesome-dv
Awesome ASIC design verification
Nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
gupta409/Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
kumarrishav14/AXI
VIP for AXI Protocol
nelsoncsc/ISP_UVM
A Framework for Design and Verification of Image Processing Applications using UVM
SystemRDL/PeakRDL
Control and status register code generator toolchain
zhajio1988/YASA
:snail:Yet Another Simulation Architecture
erihsu/INT_FP_MAC
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
Siddhi-95/AHB-to-APB-Bridge-Verification
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
dadongshangu/async_FIFO
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
SystemRDL/PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
hjking/uvm_gen
UVM Generator
postmanlabs/uvm
Universal Virtual Machine for Node and Browser
Shehab-Naga/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
kaushalmodi/custom_uvm_report_server
Customized UVM Report Server
nelsoncsc/easyUVM
A simple UVM example with DPI
Anjali-287/SPI-Interface
UVM Testbench to verify serial transmission of data between SPI master and slave
uvmdebug/uvm_debug
UVM interactive debug library
Aperture-Electronic/SystemVerilog-Bitmap-Library-AXI-Image-VIP
Bitmap Processing Library & AXI-Stream Video Image VIP
PacoReinaCampo/MPSoC-DV
Multi-Processor System on Chip verified with UVM/OSVVM/FV
verilator/uvm
Universal Verification Methodology (UVM) base libraries, with edits for Verilator
amamory-verification/uvm-basics
my UVM training projects
pulp-platform/uvm-components
Contains commonly used UVM components (agents, environments and tests).
amiq-consulting/yamm
YAMM package repository
yuravg/uvm_tb_cross_bar
SystemVerilog UVM testbench example
troyguo/dvcon_download
Download proccedings from DVCon
tallendev/uvm-eval
This serves as a repository for reproducibility of the SC21 paper "In-Depth Analyses of Unified Virtual Memory System for GPU Accelerated Computing," as well as several components of the IPDPS21 paper "Demystifying GPU UVM Cost with Deep Runtime and Workload Analysis."