Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
VerilogApache-2.0
Stargazers
- adurbin
- Alex-MannToronto, Canada
- amal-khailtash
- andrsmllr
- Balbindra
- bempelise
- ben-marshall
- cswoodruffJet Propulsion Laboratory
- dpc525
- ebertlandCerebras Systems
- elisacg
- erosh
- fafa1971Bristol, UK
- gchinnaSan Francisco Bay Area, CA
- henry23zhangShanghai
- HINATASDK
- jcpeckBay2Sierra Silicon Services, Inc.
- jdmarbleNevada, USA
- JeremyguECNU
- jlefriqueFrance
- jomonkjoy
- JunningWuCASIA
- kduncklee
- kelihlodversson
- kenyahiro
- klevin92Munich, Germany
- manu38gre
- merlionfireSingapore
- mfgmfg
- my2817
- pyroesqueColorado
- sglaserNVIDIA
- udif
- wolfmount
- zhangpengsjtu
- zopsiUSA