Juniper/open-register-design-tool

Issues

• Solving decoding congestion

  #94 opened 3 months ago by ehudeliaz
  3

• How to dump JSON file from a rdl?

  #91 opened 3 years ago by EngRaff92
  0

• Build in Debian/testing does not work

  #89 opened 3 years ago by wzab
  1

• Struct Generation not working

  #88 opened 4 years ago by abagchi
  0

• Sticky interrupt with hardware precedence and write-one-to-clear can not be cleared

  #87 opened 4 years ago by tenaliram
  0

• addressing and alignment properties of addressmap not being followed

  #85 opened 4 years ago by tenaliram
  1

• Control bit-width of address bus in addrmap

  #84 opened 4 years ago by tenaliram
  2

• Cannot get Ordt-viewer to work

  #83 opened 5 years ago by jyaghutiel
  0

• clock gating issue

  #82 opened 5 years ago by xinhui-zhang
  0

• When there is a secondary processor, decoder logic is out of sync.

  #81 opened 5 years ago by kongty
  0

• Is there an option to enable address channel for each write and read, instead of one address channel?

  #80 opened 5 years ago by kongty
  0

• How to have holding registers

  #79 opened 5 years ago by tkafafi
  0

• External Reset signals Causing RTL generation to fail

  #78 opened 5 years ago by neenuprince
  2

• gererate register verilog module has synthesis error when use Synopsys DC

  #76 opened 5 years ago by zhajio1988
  5

• ORDT coverpoints in RTL does not rename the resets to the system reset

  #77 opened 5 years ago by neenuprince
  4

• Is there an option to enable or disable the flopping of inputs and/or outputs to the RTL generated?

  #75 opened 5 years ago by neenuprince
  1

• "gated_logic_access_delay" affects access delay even if clock gating disabled

  #74 opened 5 years ago by roowatt
  2

• How to connect the APB bus to the generated verilog module？

  #73 opened 5 years ago by zhajio1988
  3

• how to write addrmap block?

  #72 opened 5 years ago by zhajio1988
  4

• Registers with intr attribute and bothedge and negedge not reseting properly

  #61 opened 5 years ago by kdloe
  4

• New commits will be made to the sdnellen fork

  #71 opened 5 years ago by sdnellen
  0

• RTl code has floating signals for HWRead SWwrite registers causing X's

  #70 opened 5 years ago by neenuprince
  2

• Register field ordering is broken.

  #69 opened 6 years ago by sjalloq
  2

• Ordt should generate an error on { sw=rw; hw=w; } with no hw we.

  #68 opened 6 years ago by sjalloq
  1

• Build error from source

  #63 opened 6 years ago by sjalloq
  2

• Incomplete reset specification on external register interface

  #62 opened 6 years ago by petenixon
  5

• XML Data Dictionary

  #52 opened 6 years ago by WebMonkey007
  2

• Interrupt enable definitions are not obeyed

  #67 opened 6 years ago by sjalloq
  5

• Reset terms are not the correct width

  #66 opened 6 years ago by sjalloq
  2

• Bug: adding a reset signal breaks ordt

  #64 opened 6 years ago by sjalloq
  4

• Unused wires generated

  #65 opened 6 years ago by sjalloq
  2

• Non-synthesizable "#1" in generated rtl

  #54 opened 6 years ago by kdloe
  6

• some External interface signals are not being reset

  #59 opened 6 years ago by neenuprince
  2

• Code generated by "resetsignal" attribute not proper

  #58 opened 6 years ago by neenuprince
  3

• Feature Request: Function to get register name

  #51 opened 6 years ago by kprabhu36
  4

• Internal error accessing SystemVerilogDefinedSignalMap generating UVM output

  #57 opened 6 years ago by ebertland
  5

• Support for "sharedextbus" and "errextbus"

  #56 opened 6 years ago by kdloe
  4

• Requesting clarification on async attribute vs use_async_resets param

  #55 opened 6 years ago by kdloe
  1

• Default bit ordering on reg fields

  #53 opened 6 years ago by natcoro
  2

• param min_data_size seems to be interpreted as the default register size for SystemRDL

  #48 opened 6 years ago by amykyta3
  2

• Feature Request : There is no way to generate the c++ driver with more than two RDL files

  #50 opened 6 years ago by kprabhu36
  3

• gradle build flow does not correctly generate SystemRDL parse code when modifying ExtParms.g4

  #41 opened 6 years ago by sdnellen
  1

• Using native uvm classes without extended classes

  #49 opened 7 years ago by Bobbyq66
  4

• RDL UDP in top-level component is silently dropped in XML output

  #47 opened 7 years ago by amykyta3
  2

• Binding RDL UDP to addrmap is not recognized

  #46 opened 7 years ago by amykyta3
  2

• Add support for all integer literal types in SystemRDL array suffixes

  #44 opened 7 years ago by amykyta3
  2

• Dummy Issue: new rdl preprocess

  #43 opened 7 years ago by gxwcxl2010
  1

• Chronologic VCS lint error: Index into non-array variable in *jrdl_decode* output file

  #42 opened 7 years ago by dtalaski
  0

• Allow use*interface on external rdl regions

  #40 opened 7 years ago by sdnellen
  0

• Rdl decr only counter still has incr

  #39 opened 7 years ago by sdnellen
  0