roowatt

Pinned Repositories

software-prototypes
Language:C00
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language:SystemVerilog831 51 55267
PeakRDL-cheader
Language:Python7 4 109
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Language:Python48 15 10037
SystemVerilog
SystemVerilog plugin for Sublime Text
Language:Python45 6 7317
software-prototypes
Language:Tcl57 6 631