TheClams/SystemVerilog

Issues

• align will add extra parenthesis and comma when there is comment after module parameter declare

  #76 opened 3 months ago by rayqqqm
  0

• Code alignment feature can lead to code breaks in certain scenarios

  #73 opened 10 months ago by rayqqqm
  1

• Hightlight mismatch when assign reg with delay

  #75 opened 3 months ago by WZ-Tong
  1

• apply color to ifdef expressions

  #71 opened 3 months ago by jotego
  1

• enumerator not showing hints when hovering

  #72 opened 3 months ago by ThePeteTree
  1

• Unable to recognize brackets

  #74 opened 10 months ago by WZ-Tong
  1

• Configurable indentation

  #70 opened a year ago by benfroelich
  1

• Latest package causes cursor lag

  #69 opened 2 years ago by cmdennett
  2

• module syntax error

  #68 opened 2 years ago by godenfreemans
  3

• Is it possible to disable or change ligature for `<=` in assignment statements?

  #67 opened 2 years ago by siddhpant
  2

• encoding problem

  #60 opened 2 years ago by rayqqqm
  4

• Tooltip is not displayed properly in latetest version(?)

  #66 opened 2 years ago by DaydreamerPP
  1

• Function regex issue

  #64 opened 2 years ago by sxu55
  2

• auto completion of module parameter not working for tag 3.1.5 in ST4

  #50 opened 2 years ago by PeteTreeUk
  9

• How to set a project?

  #52 opened 2 years ago by slumpedyeti
  3

• label for autocompletion

  #59 opened 2 years ago by xinpan1992
  1

• Alignment causes code loss/deletion

  #65 opened 2 years ago by roowatt
  1

• Alignment support blank/comment lines in the signals declaration area?

  #63 opened 2 years ago by ch3ch2sh
  2

• Alignment of logic and wire on input/output ports

  #62 opened 2 years ago by code-tangent
  2

• File encode

  #56 opened 2 years ago by godenfreemans
  2

• hovering mouse over class name in a file doesn't give the preview

  #61 opened 2 years ago by naveen2393
  1

• Syntax highlighting inconsistent for port connections of sub module

  #58 opened 2 years ago by maxbjurling
  2

• Prioritize auto-completion to reserved keywords

  #55 opened 3 years ago by perchrc
  1

• nested if-else constraints highlighting issues

  #54 opened 3 years ago by erihsu
  1

• Could you fix this, please?

  #53 opened 3 years ago by mrBitman
  1

• Hint macro define feature

  #49 opened 3 years ago by erihsu
  1

• Quartus Project -> supporting?

  #47 opened 3 years ago by ldm1417
  1

• `ifdef `else `if -> how handled?

  #51 opened 3 years ago by ldm1417
  1

• auto completion of module parameter not working for tag 3.0.9 in ST4

  #35 opened 4 years ago by PeteTreeUk
  0

• Lof of CPU usage when I type dot

  #43 opened 3 years ago by mickaelgnb
  9

• Highlight function being edited in module hierarchy

  #48 opened 3 years ago by jbshaler
  0

• How can I include external file for auto-completion with environment variables

  #45 opened 3 years ago by erihsu
  1

• Instance Name indication in the Port Declaration

  #46 opened 3 years ago by ldm1417
  1

• packed array bracket shows false syntax error

  #44 opened 3 years ago by Ali-Flt
  1

• keyword highlighting issue

  #42 opened 3 years ago by erihsu
  3

• Navigate to subfield definition in sv

  #40 opened 3 years ago by erihsu
  2

• keywords highlighting issues

  #38 opened 3 years ago by erihsu
  1

• Disable end parenthesis alignment?

  #41 opened 3 years ago by perchrc
  1

• SystemVerilog parser does not recognise scope resolution when using spaces

  #39 opened 3 years ago by nils-exibard
  0

• Several useful features for Verilog / SystemVerilog

  #37 opened 4 years ago by Fynjisx26
  0

• Incorrect syntax highlight when using `ifdef `else `endif for module instance in ST4

  #33 opened 4 years ago by nils-exibard
  0

• LSP Support?

  #36 opened 4 years ago
  0

• negedge completes to posedge

  #34 opened 4 years ago by PGAElger
  0

• Instance generator doesn't work with package declaration defined in module port list.

  #32 opened 4 years ago by mm4dd
  6

• Hierarchy viewing is not working if there are multiple classes defined in the same file

  #27 opened 4 years ago by DeeeeLAN
  1

• Is it possible to support the completion of verilog and sv's keywords?

  #29 opened 4 years ago by mczmcz
  1

• Union autocomplete doesn't work

  #30 opened 4 years ago by LS1222
  0

• ST4 Support

  #31 opened 4 years ago by roowatt
  2

• cannot turn off autocomplete

  #28 opened 4 years ago by aaleclaire
  3

• Reindenting typedefs indents poorly

  #26 opened 4 years ago by DeeeeLAN
  3