systemrdl
There are 16 repositories under systemrdl topic.
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
SystemRDL/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
sdnellen/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
OpenHisiIpCam/registers-description
HiSilicon ip camera SoCs SystemRDL registers description
hughjackson/PeakRDL-verilog
Generate verilog register file from systemRDL description
Minres/RDL-Editor
A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
MicroTCA-Tech-Lab/hectare
VHDL generator from SystemRDL
Risto97/PeakRDL-halcpp
C++ 17 Hardware abstraction layer generator from systemrdl
OpenHisiIpCam/hisi-initregtable-go-parser
HiSilicon SoC`s U-Boot initial register table parser into human readable format
Silicon1602/srdl2sv
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
SystemRDL/vscode-systemrdl
SystemRDL language support for VS Code
edaa-org/pySystemRDLModel
An abstract language model of SystemRDL written in Python.
joaohf/PeakRDL-beam
Generate BEAM (Erlang and Elixir) modules from a SystemRDL register model
SystemRDL/pygments-systemrdl
SystemRDL lexer for Pygments syntax highlighting