Internal error accessing SystemVerilogDefinedSignalMap generating UVM output
ebertland opened this issue · 5 comments
ebertland commented
This error occurs when generating UVM register model output only.
$ ordt -uvmregs out/test_uvm_reg.sv test.rdl
Open Register Design Tool, version=190321.01, input=test.rdl
*** WARNING ***: No parameters file specified. Default or inline defined parameters will be used.
Ordt: building UVM regs...
*** ERROR ***: Attempted to access SystemVerilogDefinedSignalMap prior to initialization - insure map is defined in concrete child class
Ordt exited due to error Wed Apr 10 18:08:00 PDT 2019
A work-around is to also generate RTL using -systemverilog.
$ ordt -systemverilog out/test_rtl/ -uvmregs out/test_uvm_reg.sv test.rdl
Open Register Design Tool, version=190321.01, input=test.rdl
*** WARNING ***: No parameters file specified. Default or inline defined parameters will be used.
Ordt: building systemverilog...
Ordt: writing systemverilog file out/test_rtl/my_cntrs_pio.sv...
Ordt: writing systemverilog file out/test_rtl/my_cntrs_jrdl_logic.sv...
Ordt: writing systemverilog file out/test_rtl/my_cntrs_jrdl_decode.sv...
Ordt: building UVM regs...
Ordt: writing UVM regs file out/test_uvm_reg.sv...
Ordt complete Wed Apr 10 18:05:53 PDT 2019
ebertland commented
Commenting out u.value->incr = l.value->overflow; avoids the problem, so it is related to signal assignments. That's probably obvious based on the error message.
ebertland commented
This test fails on HEAD of master (550847c) and on the latest release jar (version 181009.01).
It passes on the previous release jar (version 180502.01). My best guess is that this bug was introduced during refactoring in August 2018.
sdnellen commented
Committed fix in 190411.01.
ebertland commented
The new version works for me. Closing.