asic

There are 385 repositories under asic topic.

  • skywater-pdk

    google/skywater-pdk

    Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

    Language:Python3.3k159275427

  • openhwgroup/cva6

    The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

    Language:Assembly2.6k941.1k829
  • serv

    olofk/serv

    SERV - The SErial RISC-V CPU

    Language:Verilog1.6k4366228

  • The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Language:Python1.6k64970401

  • ultraembedded/riscv

    RISC-V CPU Core (RV32IM)

    Language:Verilog1.5k5318265

  • clash-lang/clash-compiler

    Haskell to VHDL/Verilog/SystemVerilog compiler

    Language:Haskell1.5k531k163

  • pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    Language:SystemVerilog1.4k40125311

  • ultraembedded/biriscv

    32-bit Superscalar RISC-V CPU

    Language:Verilog1.1k3225187

  • siliconcompiler/siliconcompiler

    Modular hardware build system

    Language:Python1.1k24347110

  • ucb-bar/gemmini

    Berkeley's Spatial Array Generator

    Language:Scala1.1k32202216

  • esig/dss

    Digital Signature Service : creation, extension and validation of advanced electronic signatures

    Language:Java9021230394

  • riscvarchive/riscv-cores-list

    RISC-V Cores, SoC platforms and SoCs

    894574212

  • ultraembedded/cores

    Various HDL (Verilog) IP Cores

    Language:Verilog832495221

  • VUnit/vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

    Language:VHDL78950635282

  • VLSI-EDA/PoC

    IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

    Language:VHDL5895855108

  • zssloth/Embedded-Neural-Network

    collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

    557904120

  • pulp-platform/ara

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

    Language:C46121203144

  • rggen/rggen

    Code generation tool for control and status registers

    Language:Ruby4211417755
  • gf180mcu-pdk

    google/gf180mcu-pdk

    PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

    Language:Makefile389214958

  • secworks/aes

    Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

    Language:Verilog386269134

  • slaclab/surf

    A huge VHDL library for FPGA development

    Language:VHDL382481869

  • dpretet/async_fifo

    A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

    Language:Verilog37711683

  • tensil-ai/tensil

    Open source machine learning accelerators

    Language:Scala375102830

  • sld-columbia/esp

    Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

    Language:C36425122119

  • troyguo/awesome-dv

    Awesome ASIC design verification

    32311169

  • furrtek/DMG-CPU-Inside

    Reverse-engineered schematics for DMG-CPU-B

    320188219

  • pulp-platform/mempool

    A 256-RISC-V-core system with low-latency access into shared L1 memory.

    Language:C28981049

  • pulp-platform/cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    Language:Verilog283152661

  • tymonx/logic

    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

    Language:SystemVerilog28131160

  • efabless/openlane2

    The next generation of OpenLane, rewritten from scratch with a modular architecture

    Language:Python2771330959

  • abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

    IC implementation of Systolic Array for TPU

    Language:Verilog2753132

  • SystemRDL/systemrdl-compiler

    SystemRDL 2.0 language compiler front-end

    Language:C++2602517674

  • anselal/antminer-monitor

    Cryptocurrency ASIC mining hardware monitor using a simple web interface

    Language:Python23734181144

  • trilomix/GDS3D

    GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.

    Language:C++23072138

  • cornell-zhang/allo

    Allo: A Programming Model for Composable Accelerator Design

    Language:Python221117537

  • masc-ucsc/livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

    Language:FIRRTL2202817950