asic
There are 434 repositories under asic topic.
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
olofk/serv
SERV - The SErial RISC-V CPU
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
siliconcompiler/siliconcompiler
Modular hardware build system
ucb-bar/gemmini
Berkeley's Spatial Array Generator
splinedrive/kianRiscV
RISC-V XV6/Linux SoC, marchID: 0x2b
esig/dss
Digital Signature Service : creation, extension and validation of advanced electronic signatures
riscvarchive/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
ultraembedded/cores
Various HDL (Verilog) IP Cores
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
VLSI-EDA/PoC
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
zssloth/Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
pulp-platform/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
google/gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
rggen/rggen
Code generation tool for control and status registers
slaclab/surf
A huge VHDL library for FPGA and digital ASIC development
secworks/aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
sld-columbia/esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
tensil-ai/tensil
Open source machine learning accelerators
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
troyguo/awesome-dv
Awesome ASIC design verification
furrtek/DMG-CPU-Inside
Reverse-engineered schematics for DMG-CPU-B
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
pulp-platform/mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
cornell-zhang/allo
Allo: A Programming Model for Composable Accelerator Design
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
unihd-cag/skillbridge
A seamless python to Cadence Virtuoso Skill interface
anselal/antminer-monitor
Cryptocurrency ASIC mining hardware monitor using a simple web interface