Issues
- 1
Wrong signal assigment
#1107 opened by antoniobergnoli - 2
help with Tcl command using Ruckus
#1052 opened by tulliog - 1
Error in FifoMux.vhd when RD_DATA_WIDTH_G < WR_DATA_WIDTH_G and rd_en is a pulse
#1017 opened by sgoadhouse - 3
Changes to base/ram/ruckus.tcl in v2.31.1 incorrectly prevents builds with XPM true dual port FIFO using Vivado 2019.1
#997 opened by sgoadhouse - 3
use surf in a project
#916 opened by Ahmad-Zaklouta - 1
Inferred AxiDualPortRam XPM synth mode fails
#851 opened by jmdewart - 1
distribured AxiDualPortRam latency wrong
#850 opened by jmdewart - 6
- 1
SlvDelayFifo wraparound
#673 opened by thatweaver - 2
adc32rf45.vhd width mismatch
#589 opened by jmdewart - 1
Pgp3GthUsWrapper.vhd SYNTH_MODE_G not declared
#590 opened by jmdewart - 4
How can i build a example project?
#545 opened by Jzone315 - 2
GTX7 RXCHBONDSLAVE and Clock Correction
#55 opened by PsiStarPsi