slaclab/surf

Wrong signal assigment

Closed this issue · 1 comments

antoniobergnoli commented

surf/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd

Line 335 in c9f42ce

clkFbOut <= clkFbIn;

Lefthand signal to be exchanged with rigthhand in assignment

ruck314 commented

@antoniobergnoli Pull Request #1108 will fix this. Thanks for reporting this bug.