hdl
There are 598 repositories under hdl topic.
amaranth-lang/amaranth
A modern hardware definition language and toolchain based on Python
langhuihui/monibuca
🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
analogdevicesinc/hdl
HDL libraries and projects
aappleby/metroboy
A repository of gate-level simulators and tools for the original Game Boy.
drom/awesome-hdl
Hardware Description Languages
m-labs/nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
Nuand/bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
pymtl/pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
intel/rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
tensil-ai/tensil
Open source machine learning accelerators
Kitware/VeloView
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
analogdevicesinc/plutosdr-fw
PlutoSDR Firmware
slaclab/surf
A huge VHDL library for FPGA development
viduraakalanka/HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
spamegg1/reviews
Reviewing some online CS courses I took
chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
masc-ucsc/livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
yupferris/kaze
An HDL embedded in Rust.
kactus2/kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
suoto/hdl_checker
Repurposing existing HDL tools to help writing better code
kevinpt/symbolator
HDL symbol generator
catkira/open5G_phy
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
im-tomu/fomu-workshop
Support files for participating in a Fomu workshop
aappleby/metron
A C++ to Verilog translation tool with some basic guarantees that your code will work.
furrtek/SiliconRE
Custom chips reverse-engineered from silicon
google/pcbdl
PCB Design Language: A programming way to design schematics.
1801BM1/cpu11
Revengineered ancient PDP-11 CPUs, originals and clones
bogdanvuk/pygears
HW Design: A Functional Approach
codingonion/awesome-cuda-tensorrt-fpga
🔥🔥🔥 A collection of some awesome public NVIDIA CUDA, cuBLAS, cuDNN, TensorRT, AMD ROCm and FPGA projects.
mciepluc/cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
gateware-ts/gateware-ts
Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
asyncvlsi/act
ACT hardware description language and core tools.