m-labs/nmigen

Issues

• For loops in Nmigen

  #350 opened 2 years ago by ParasVekariya
  0

• No clk being generated

  #349 opened 3 years ago by mayank-kabra2001
  0

• nmigen install error

  #348 opened 3 years ago by ZhangPeterGree
  1

• Does nmigen support I2C master ?

  #347 opened 3 years ago by jimmymagemtek
  1

• Want to know some details of the back

  #346 opened 3 years ago by ekikun
  1

• Improve readability of assignments and add contexts for clock domains

  #345 opened 3 years ago by ildus
  0

• Please add details that this repository is obsolete/not longer maintained anymore for new comer

  #342 opened 4 years ago by bvernoux
  3

• Python simulator hangs or throws when trying to drive reset from testbench

  #341 opened 4 years ago by hansfbaier
  1

• negative values support in Switch-Case

  #340 opened 4 years ago by weshu
  1

• Allow more flexibility in FHDLTestCase assertFormal

  #336 opened 4 years ago by DonaldKellett
  0

• hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa)

  #310 opened 5 years ago
  5

• Signal decoder inference for Enums doesn't work for Layout members

  #333 opened 4 years ago by shawnanastasio
  0

• Can't generate verilog for blinky example: Only signals may be added as ports

  #332 opened 4 years ago by shawnanastasio
  1

• lambdasoc analysis & synthesis got error on intel platform.

  #331 opened 4 years ago by franz-git
  0

• Generating async negedge reset

  #329 opened 4 years ago by tariqafzal
  0

• Hierarchical Redundancy in emitted Verilog

  #328 opened 4 years ago by BracketMaster
  1

• Bus arbiter broken after synthesis

  #325 opened 4 years ago by strobo5
  1

• Can I create an active-low (asynchronous) reset?

  #327 opened 4 years ago by hofstee
  0

• Internal Oscillator Usage ICE40

  #321 opened 4 years ago by jchidley
  7

• Installation fails if wheel not installed

  #323 opened 4 years ago by alanvgreen
  3

• Release timeline

  #322 opened 5 years ago by FFY00
  2

• Initial Class: ValueError: call stack is not deep enough

  #318 opened 5 years ago by goktug97
  4

• There's no explicit way to convert between signed <-> unsigned values

  #292 opened 5 years ago by Maykeye
  1

• vendor.xilinx_7series: Vivado TIMING-2 Warning

  #301 opened 5 years ago by peteut
  4

• Index a signal with a slice from another signal

  #319 opened 5 years ago by rnd2
  2

• Unclear error message when using an Array as port

  #290 opened 5 years ago by Ravenslofty
  0

• FSM with transition to nonexistent state should not elaborate

  #315 opened 5 years ago by awygle
  1

• Assigning local domain with different name

  #282 opened 5 years ago by Fatsie
  0

• Need a way to attach attributes to memories

  #291 opened 5 years ago by JarrettBillingsley
  0

• Unable to Build and flash my board.

  #320 opened 5 years ago by teezzan
  9

• Using Python to Formal Verify Verilog and VHDL Files

  #317 opened 5 years ago by goktug97
  4

• Case pattern syntax improvement

  #316 opened 5 years ago by porglezomp
  2

• Misleading error when trying to use self.comb when inheriting from Module

  #286 opened 5 years ago by asumagic
  2

• Assignment to a Record with zero-width fields generates invalid Verilog

  #312 opened 5 years ago by jfng
  3

• Usability? Can we warn if a Statement is never assigned to a domain?

  #303 opened 5 years ago by RobertBaruch
  2

• AssertionError with strange Switch

  #305 opened 5 years ago by Ravenslofty
  1

• Support for non integer connector / ressource 'numbers'

  #311 opened 5 years ago by anuejn
  2

• Signal.__doc__: Mention `range`'s `Shape.cast`able Variant

  #288 opened 5 years ago by peteut
  1

• nmigen generates invalid RTLIL with negative shifts

  #302 opened 5 years ago by Ravenslofty
  1

• if m.If(...): is silently dropped

  #284 opened 5 years ago by Stary2001
  0

• AssertionError domain.name not in self.domains

  #307 opened 5 years ago by nicolas-robin
  4

• How to pass yosys_opts to LatticeICE40Platform?

  #314 opened 5 years ago by RobertBaruch
  2

• Support Platforms that include an existing design and expose interface to that design as Resource

  #308 opened 5 years ago by smunaut
  0

• ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances

  #304 opened 5 years ago by povauboin
  3

• Output enable for Intel platform on multi I/O pins

  #297 opened 5 years ago by schwigi
  6

• Add EnableSignal, useful for making Instances compatible with EnableInserter

  #285 opened 5 years ago by Fatsie
  21

• (Verilog) nMigen should provide better information about original source code locations

  #293 opened 5 years ago by Maykeye
  3

• Finding out what resources an nMigen module uses in the output design

  #289 opened 5 years ago by JarrettBillingsley
  12

• Document simulator commands

  #287 opened 5 years ago by Ravenslofty
  1

• Record.like() should be a classmethod, not staticmethod.

  #283 opened 5 years ago by kbob
  3