mayank-kabra2001
Adaptable to perform well in challenging environments. Ambitious to make an impact on the real world by leveraging my potential to solve real life problems.
International institute of information technologyBangalore, India
Pinned Repositories
5-stage-processor
AES-implementation-in-c-
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
awesome-hdl
Hardware Description Languages
boost
Branch-prediction
bsc-1
Bluespec Compiler (BSC)
Processors
Summer_blog
WARPV-TSMC
mayank-kabra2001's Repositories
mayank-kabra2001/WARPV-TSMC
mayank-kabra2001/5-stage-processor
mayank-kabra2001/Processors
mayank-kabra2001/Summer_blog
mayank-kabra2001/AES-implementation-in-c-
mayank-kabra2001/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
mayank-kabra2001/boost
mayank-kabra2001/caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
mayank-kabra2001/caravel-lite
mayank-kabra2001/caravel_pico
mayank-kabra2001/CircuitVerse
CircuitVerse Primary Code Base
mayank-kabra2001/fpga_lab
mayank-kabra2001/iiitb_riscv32im5
mayank-kabra2001/images
mayank-kabra2001/Leetcode-Solutions
My Submissions for over 1200 Leetcode Problems
mayank-kabra2001/LeNet-5-PyTorch
Implementation of LeNet-5 architecure on CPU and GPU using PyTorch
mayank-kabra2001/LF-Building-a-RISC-V-CPU-Core
mayank-kabra2001/litex
Build your hardware, easily!
mayank-kabra2001/makerchip_examples
mayank-kabra2001/mobilenet
TensorFlow 2 implementation of MobileNet (see https://arxiv.org/abs/1704.04861)
mayank-kabra2001/MobilenetV3-Tensorflow
the multi-GPUs implementation of mobilenet v3 in tensorflow with tf.layers
mayank-kabra2001/models
Models and examples built with TensorFlow
mayank-kabra2001/My-BlogPost
mayank-kabra2001/My-Portfolio
mayank-kabra2001/prim-benchmarks-mine
mayank-kabra2001/Pygame
mayank-kabra2001/raptor
Arm Cortex-M0 based Customizable SoC for IoT Applications
mayank-kabra2001/risc-v-core
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
mayank-kabra2001/tensor-core-viz
mayank-kabra2001/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.