yosys
There are 161 repositories under yosys topic.
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
cariboulabs/cariboulite
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
nturley/netlistsvg
draws an SVG schematic from a JSON netlist
olofk/edalize
An abstraction library for interfacing EDA tools
m-labs/nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
zachjs/sv2v
SystemVerilog to Verilog conversion
efabless/caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
apfaudio/eurorack-pmod
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
PyFPGA/pyfpga
A Python package to use FPGA development tools programmatically.
efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
lushaylabs/tangnano9k-series-examples
Examples for the Lushay Labs tang nano 9k series
akilm/Physical-Design
Physical Design Flow from RTL to GDS using Opensource tools.
forflo/yodl
A VHDL frontend for Yosys
chipsalliance/fpga-tool-perf
FPGA tool performance profiling
ECP5-PCIe/ECP5-PCIe
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
scarv/xcrypto
XCrypto: a cryptographic ISE for RISC-V
dadamachines/doppler
Arduino compatible – Cortex M4F & FPGA Development Board
stnolting/neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
chipsalliance/yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
multigcs/LinuxCNC-RIO
RealtimeIO for LinuxCNC based on an FPGA
mattvenn/fpga-sdft
sliding DFT for FPGA, targetting Lattice ICE40 1k
YoWASP/yosys
Unofficial Yosys WebAssembly packages
tmeissner/psl_with_ghdl
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
SymbiFlow/sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
ben-marshall/croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
vmunoz82/eda_tools
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
ghdl/docker
Scripts to build and use docker images including GHDL
tmeissner/formal_hw_verification
Trying to verify Verilog/VHDL designs with formal methods and tools
embedded-explorer/Open-Source-RTL-Design
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
chili-chips-ba/openXC7-TetriSaraj
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
racerxdl/tangnano-yosys-hello
Sipeed Tang Nano Fully Opensource Toolchain Ledblink
maazm007/vsdsquadron-mini-internship
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
mmicko/enigmaFPGA
Enigma in FPGA
shrine-maiden-heavy-industries/torii-hdl
A Python-based HDL and framework for silicon-based witchcraft
osresearch/risc8
Mostly AVR compatible FPGA soft-core
scarv/scarv-cpu
SCARV: a side-channel hardened RISC-V platform