efabless/caravel_mpw-one

Issues

• Net types not explicitly declared, but default_nettyp set to none

  #55 opened 4 years ago by heavySea
  1

• Error of missing module and re-definition

  #88 opened 3 years ago by AyaseErii
  0

• User project needs reset pin

  #86 opened 3 years ago by RTimothyEdwards
  0

• Generating of DFFRAM macro fails during Power Delivery Network generation

  #84 opened 3 years ago by boehmerst
  0

• Enable Pico Co-Processor Interface?

  #35 opened 4 years ago by sjkelly
  2

• Typo in the "about" section of the GitHub project page

  #79 opened 3 years ago by JohnPhilipBiggs
  0

• Stuck at certain steps using caravel_user_project and caravel_user_project_analog.

  #71 opened 3 years ago by peijunh
  1

• spi_* signals in Pin Description table not appearing in Pinout table

  #70 opened 3 years ago by Piyush3dB
  1

• Gate Sim Issue: user_project_wrapper Port name mismatch between RTL & Gate level caravel.v

  #66 opened 3 years ago by dineshannayya
  2

• make run-precheck hangs at XOR check

  #64 opened 3 years ago by techeraj-osh
  2

• Emulated substrate ground shortening results in undefined behaviour in other simulators

  #54 opened 4 years ago by heavySea
  1

• Interrupt IO in user_project_wrapper

  #52 opened 3 years ago by KPrabs106
  1

• Reindex the analog_io pins on the user_project_wrapper

  #45 opened 3 years ago by ax3ghazy
  1

• Be explicit about the SRAM_1 port 1 connections

  #44 opened 3 years ago by ax3ghazy
  1

• SRAM_1 in storage macro has floating inputs

  #42 opened 3 years ago by d-m-bailey
  1

• simpleuart enable bug

  #39 opened 3 years ago by baberali-lm
  1

• Unused Inputs to Management Area

  #17 opened 3 years ago by yrrapt
  1

• Caravele doesn't provide internal picorv32 interrupts!

  #11 opened 3 years ago by jean-m-cyr
  4

• Redirect https://caravel-docs.readthedocs.io/en/latest/ to the right place

  #72 opened 3 years ago by mithro
  0

• Synthesis error with openlane

  #69 opened 3 years ago by ankitwahane
  6

• Resevered System Verilog variable (clocking) used inside mgmt_core.v

  #68 opened 3 years ago by dineshannayya
  0

• Caravel Gate Level simulation setup is broken

  #67 opened 3 years ago by dineshannayya
  2

• IRQ input pin needs a glitch filter

  #62 opened 4 years ago by RTimothyEdwards
  0

• PDK installation for several variants

  #59 opened 4 years ago by thesourcerer8
  0

• LVS/CVC issues with caravel modules

  #41 opened 4 years ago by d-m-bailey
  2

• Multi-master Wishbone bus unsupported

  #43 opened 4 years ago by jean-m-cyr
  1

• No link to the documentation at https://caravel-docs.readthedocs.io/en/moving-to-rst/index.html

  #38 opened 4 years ago by mithro
  3

• Syntax Tests in verilog/dv/user_proj_exmaple

  #36 opened 4 years ago
  1

• add a clock divider

  #37 opened 4 years ago by mattvenn
  0

• Cannot harden design using option 2 and no macros

  #22 opened 4 years ago by SweeperAA
  3

• Create a quickstart document for the Caravel project

  #32 opened 4 years ago by glatosinski
  1

• Create a script for generating Caravel chip diagram using netlistsvg

  #30 opened 4 years ago by glatosinski
  1

• Move the documentation from PS/PDF format to RST

  #26 opened 4 years ago by glatosinski
  1

• Documentation Improvement Notes

  #23 opened 4 years ago by mkkassem
  0

• [CI] periodically print progress information during DRC check

  #16 opened 4 years ago by ohAitch
  1

• Cannot simulate caravel module due to “`defaultnet_type none” and undeclared nets

  #3 opened 4 years ago by dan-rodrigues
  9

• Synthesis error with openlane develop branch

  #1 opened 4 years ago by sjkelly
  1