Synthesis error with openlane develop branch

[sjkelly]

openlane: c077f963c23b53e2cd39656e3d21689537110707
caravel: 297a6cf (HEAD as of this issue)
skywater-pdk: 1ce480d61120895462adc03df617d39de7a0f76e (Master~4, pulled by openlane build)

[INFO]: Running Synthesis...

<snip>

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
ERROR: Module `\PASS' referenced in module `\DFFRAM' in cell `\MUX' is not part of the design.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth_top.tcl -l /project/openlane/DFFRAM/runs/DFFRAM/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log

    while executing
"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l $::env(yosys_log_file_tag).log  |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 22)
    invoked from within
"run_yosys"
    (procedure "run_synthesis" line 4)
    invoked from within
"run_synthesis"
    (procedure "run_non_interactive_mode" line 11)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: DFFRAM] Error 1

[sjkelly]

Seems to be fixed on latest Openlane and caravel!