openram

There are 6 repositories under openram topic.

  • skywater-pdk

    google/skywater-pdk

    Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

    Language:Python3.3k161276431

  • The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Language:Python1.6k59973407

  • efabless/caravel

    Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

    Language:Verilog3612024199

  • efabless/caravel_mpw-one

    Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

    Language:Verilog1361737141

  • ShonTaware/SRAM_SKY130

    Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

    Language:SourcePawn794115

  • SinaKarvandi/hardware-design-stack

    The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

    Language:VHDL10102