picorv32

efabless/caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

akilm/Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

wuhanstudio/picorv32_tang

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

antonson-j1/SHA256-Accelerator-Hardware

This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog and synthesized using Yosys Open Synthesis Suite. The optimized designs are then compared with a base-line C implementation in software. Hash functions are used to securely store passwords, to quickly store and retrive data, and also to check if a file/message is corrupted.

michg/riscv32_lcc

wuhanstudio/picorv32_EG4S20

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

michg/riscv32_beluga

c compiler beluga with riscv32 backend

wuhanstudio/picorv32_MXO2

A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)

Jesus89/picorv32-c-examples

C examples for picorv32 CPU

MuratovAS/icesugar-riscv

A RiscV verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

majorlin/xloader

Xilinx FPGA loader

atx/gps-freq-counter

Frequency counter using a GPS receiver PPS output as its reference

brown9804/NexysDDR4-RISC-V_picorv32

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-fayizferosh

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

2uger/tiny_soc

Simple implementation of SOC around PicoRV32 soft core.

JOKleinGe1/min_sys_riscv

Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile

JunnanLi/picoSoC

SoC of PicoRV32i

lnis-uofu/OpenFPGA-Softcores

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

michg/cparserlibfirm_riscv32

tmahlburg/picosoc-basys3

Wrapper module for the PicoSoC to support the Digilent Basys 3

splinedrive/TangNano-9K-example

TangNano-9K-example project with kianRiscV cpu