Pinned Repositories
caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_board
caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_user_project
https://caravel-user-project.readthedocs.io
caravel_user_project_analog
mpw_precheck
openframe_timer_example
Example digital project for the Efabless Caravel "openframe" harness
OpenLane
This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Efabless's Repositories
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
efabless/volare
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
efabless/cace
Circuit Automatic Characterization Engine
efabless/caravel_mgmt_soc_litex
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
efabless/sky130_klayout_pdk
Skywaters 130nm Klayout PDK
efabless/ipm
Open-source IPs Package Manager (IPM)
efabless/EF_UART
Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
efabless/nix-eda
Nix derivations for EDA tools
efabless/skywater-pdk-libs-sky130_fd_pr
efabless/BusWrap
efabless/caravel_user_sram
efabless/openframe_timer_example
Example digital project for the Efabless Caravel "openframe" harness
efabless/EF_SRAM_1024x32
efabless/EF_TMR32
A 32-bit Timer/Counter/Capture/PWM Soft IP (Verilog)
efabless/caravel-sim-infrastructure
efabless/EF_GPIO8
A generic 8-bit General Purpose I/O (GPIO) Peripheral
efabless/EF_PSRAM_CTRL
A Quad I/O SPI Pseudo Static RAM (PSRAM) Controller
efabless/EF_QSPI_XIP_CTRL
A QSPI XiP Flash Controller with a Direct Mapped Cache
efabless/caravel_mini_sram
efabless/EF_AES
efabless/EF_I2C
efabless/EF_I2S
Two-wire I2S synchronous serial interface, compatible with I2S specification.
efabless/EF_QSPI_FLASH_WRITER
efabless/EF_SHA256
efabless/EF_SPI
efabless/EF_USB_CDC_WRAPPER
efabless/EF_WDT32
A simple WatchDog Timer (WDT)
efabless/openlane-metrics
Repository to store metric results for OpenLane 2.0.0+
efabless/openlane2-ci-designs
Continuous Integration Designs for OpenLane 2.0.0 or higher
efabless/sky130_ak_ip__comparator
Comparator in sky130 by Andrew Kang (Chipalooza challenge 2024)