Pinned Repositories
caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
caravel_board
caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_user_project
https://caravel-user-project.readthedocs.io
caravel_user_project_analog
frigate-os
mpw_precheck
OpenLane
This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Efabless's Repositories
efabless/caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
efabless/caravel_user_project
https://caravel-user-project.readthedocs.io
efabless/mpw_precheck
efabless/ipm
Open-source IPs Package Manager (IPM)
efabless/nix-eda
Nix derivations for EDA tools
efabless/nldiff
Simple netlist comparison utility
efabless/Caravel_on_FPGA
efabless/caravel_user_sram
efabless/frigate-os
efabless/openframe_timer_example
Example digital project for the Efabless Caravel "openframe" harness
efabless/EF_PSRAM_CTRL
A Quad I/O SPI Pseudo Static RAM (PSRAM) Controller
efabless/EF_SRAM_1024x32
efabless/caravel_SI_testing
efabless/IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
efabless/sky130_ef_ip__rdac3v_8bit
8-bit resistor ladder DAC with 3.3V output range
efabless/central_CI
efabless/chipignite_discover
efabless/EF_AES
efabless/EF_SHA256
efabless/frigate_analog
The analog signal processing and timing frontend subsystems for the Frigate harness chip
efabless/frigate_user_project
efabless/openlane-metrics
Repository to store metric results for OpenLane 2.0.0+
efabless/openlane2-ci-designs
Continuous Integration Designs for OpenLane 2.0.0 or higher
efabless/openlane2-step-unit-tests
Step-specific Unit Tests for OpenLane 2.0.0+
efabless/sky130_ef_ip__adc3v_12bit
12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
efabless/sky130_ef_ip__samplehold
Analog 3.3V sample and hold circuit, with buffered output
efabless/sky130_ef_ip__simple_por
Simple PoR based on an RC filter
efabless/sky130_ef_ip__template
A template repository for analog designs to ensure consistency and interoperability between IP blocks.
efabless/timing-scripts