Pinned Repositories
caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_board
caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_user_project
https://caravel-user-project.readthedocs.io
caravel_user_project_analog
mpw_precheck
openframe_timer_example
Example digital project for the Efabless Caravel "openframe" harness
OpenLane
This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Efabless's Repositories
efabless/caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
efabless/timer-tutorial
Source files for the timer-tutorial
efabless/globalfoundries-pdk-libs-gf180mcu_fd_pv
efabless/caravel_SI_testing
efabless/skywater-pdk-libs-sky130_fd_sc_hs
efabless/skywater-pdk-libs-sky130_fd_sc_hvl
efabless/skywater-pdk-libs-sky130_fd_sc_ms
efabless/usb_cdc
Full Speed USB interface for FPGA and ASIC designs
efabless/libparse-python
Python wrapper around Yosys's `libparse` module
efabless/sky130_rodovalho_ip__lpopamp
Low-power operational amplifier by Luis Henrique Rodovalho (Chipalooza challenge 2024)
efabless/skywater-pdk-libs-sky130_fd_sc_hdll
efabless/tt-fpga-demo
efabless/tt-fpga-hdl-demo
efabless/utilities
A repo for various EDA related utilities
efabless/caravel_mgmt_soc_gf180mcu
This repository is the GF180MCU port of management core for Caravel. For more information about the Caravel management SoC, see https://github.com/efabless/caravel_mgmt_soc_litex.
efabless/EF_QSPI_FLASH_CTRL
efabless/EF_QSPI_FLASH_WRITER
efabless/extra_be_checks
Extra backend checks for sky130
efabless/globalfoundries-pdk-libs-gf180mcu_fd_io
IO and periphery cells for the GF180MCU provided by GlobalFoundries.
efabless/I2C
Verilog I2C interface for FPGA implementation
efabless/MS_QSPI_XIP_CACHE
AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
efabless/sky130_ajc_ip__overvoltage
Overvoltage detector for sky130 process by Robin Tsang (Chipalooza challenge 2024)
efabless/sky130_ajc_ip__por
Power-on-reset for SKY130 by Robin Tsang (Chipalooza challenge 2024)
efabless/sky130_iic_ip__sar_adc1
Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
efabless/skywater-pdk-libs-sky130_fd_sc_lp
efabless/spm_user_project_wrapper
https://caravel-user-project.readthedocs.io
efabless/SW_AES
efabless/SW_SHA256
efabless/tt06-verilog-template
Submission template for Tiny Tapeout 06 - Verilog HDL Projects
efabless/tt_ml_test