Caravele doesn't provide internal picorv32 interrupts!
jean-m-cyr opened this issue · 4 comments
The Caravel SOC design has one external interrupt pin, but doesn't seem to provide any accessible internal interrupt ports for internal wishbone slave peripheral user projects that would need them. It would be a shame to have to drive an extra output pin just to loop it back to the external interrupt input pin.
You're wanting to have the user project be able to raise an interrupt on the managment SoC through the wishbone bus?
I believe that is the feature request seen on slack, correct.
Not over the bus. Wishbone doesn't support it. More likely one or two unused wires into the interrupt controller. Something akin to the user_clock2 signal user project port.
This issue was corrected on the caravel version for MPW-two, so I am closing this issue now.