Emulated substrate ground shortening results in undefined behaviour in other simulators

[heavySea]

The mgmt_protect_hv.v of the Buffer Protection contains a section to emulate the substrate shortening ground together, which was introduced with 4d78284.

assign vssa2 = vssa1;
assign vssa1 = vssd;

It is stated to be required for LVS.

In all testbenches there is only one source of ground, wire VSS = 1'b0;. In simulators other than iverilog (i.a. Questa/Modelsim) this and the above assignment will result in an undefined behavior, since the signal is essentially assigned to itself multiple times.

There are two possible solutions:

1. Defining separate ground signals in the testbenches (Although in reality it is most probably the same ground?)
2. Exclude this part from simulations since it is stated to be required for LVS only. This could be done like this

`ifndef SIM
    assign vssa2 = vssa1;
    assign vssa1 = vssd;
`endif

Note, this is not reproducible with iverilog!

[RTimothyEdwards]

Magic was updated since the issue was raised to better extract independent substrate domains. That was accompanied by a layout change to the management protect block to isolate the ground domains. That means that the extracted layout now keeps the ground domains separate, and the assignments should not be needed for LVS, so this needs to be revisited.