yrrapt

Analogue/Digital ASIC design, RF/SDR, High Reliability and Space

The Netherlands

Pinned Repositories

payload-dmt
Digital Multiplexing Transponder
Language:Jupyter Notebook1 3 31
system-definition
Top level system definition of the satellite design
Language:HTML5 4 01
amsat_txrx_ic
An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
Language:Jupyter Notebook70 13 011
analog_sim
A Spice simulation interface
Language:Python9 4 03
analogue_design_example
An example of analogue design using open source IC design tools
Language:Shell29 3 07
caravel_amsat_txrx_ic
Language:Verilog29 4 06
genetic_algorithm_optimiser
General purpose Genetic Algorithm optimiser library
Language:Python1 2 00
Genius-TCAD-Open
Open-source version of the Genius Semiconductor Device Simulator
Language:C++2 0 02
inductor-generator
Language:Python9 5 04
qucs_s
Qucs-S is spin-off of Qucs. See https://ra3xdh.github.io/ for details.
Language:C++0 1 00

yrrapt's Repositories

yrrapt/amsat_txrx_ic
An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
Language:Jupyter Notebook70 13 011
yrrapt/analogue_design_example
An example of analogue design using open source IC design tools
Language:Shell29 3 07
yrrapt/caravel_amsat_txrx_ic
Language:Verilog29 4 06
yrrapt/analog_sim
A Spice simulation interface
Language:Python9 4 03
yrrapt/inductor-generator
Language:Python9 5 04
yrrapt/caravel_amsat_txrx_ic_mpw2
Language:Shell3 1 01
yrrapt/sky130_setup
Ubuntu scripts that are used for setting up your machine for Sky130 designs.
Language:Shell3 3 04
yrrapt/analogue_ic_template
A template analogue IC project repository
Language:Shell2 2 03
yrrapt/icfab
Language:VHDL2 2 02
yrrapt/cacd
Space CACD
Language:C1 0 0
yrrapt/dvb_fpga
RTL implementation of components for DVB-S2
Language:VHDL1 1 0
yrrapt/librecell
Language:Python1 3 01
yrrapt/xschem-conda-recipe
Attempt at creating conda recipe for xschem
Language:Shell1 1 1
yrrapt/adi_adrv9371_zc706
adi's adrv9371 example integration with DVB-S2 IP
Language:Verilog0 0
yrrapt/analogue_asic_experiments
Language:Shell1 01
yrrapt/bag
BAG framework
Language:Python0 01
yrrapt/cbag
A C++ VLSI circuit schematic and layout database library
Language:C++0 0
yrrapt/gate_drive_discussion
Language:Jupyter Notebook1 0
yrrapt/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Language:SystemVerilog1 0
yrrapt/klayout_setup
Tools and settings for KLayout
1 01
yrrapt/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Language:Verilog1 0
yrrapt/pybag
Language:C++0 0
yrrapt/pybind11
Seamless operability between C++11 and Python
Language:C++0 0
yrrapt/pybind11_generics
generics library for pybind11
Language:C++0 0
yrrapt/pyems
High-level python interface to OpenEMS with automatic mesh generation
Language:Python1 0
yrrapt/simulate_7seg
Language:Makefile0 0
yrrapt/sky130_analog_testcases
yrrapt/skywater-pdk-libs-sky130_fd_pr
0 0
yrrapt/xschem-gaw
gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms
Language:C0 0
yrrapt/yrrapt.github.io
Language:SCSS1 0