Caravel Gate Level simulation setup is broken

[dineshannayya]

Verification command for GL is not working inside the docker,
simulation is running in RTL mode only for BOTH -SIM=RTL and -SIM=GL command.

RTL command : make verify-wb_port -SIM=RTL
GL Command: make verify-wb_port -SIM=GL

For both case iverilog command executed is for RTL compile command without GL switch:

iverilog -DFUNCTIONAL -DSIM 

Look like SIM variable export function inside the docker is not working.

When I tried direct GL simulation, Test fails with internal core boot is working, but IO pad are going unknown.

Look like Caravel Gate Level Simulation setup is broken.

[dineshannayya]

Ignore this issue, look like there is typo in the command
Actual command need to be make verify-wb_port SIM=GL

[dineshannayya]

Ignore this issue, look like there is typo in the command
Actual command need to be make verify-wb_port SIM=GL