Issues
- 7
Verify windows support
#3 opened by rodrigomelo9 - 1
Re-add support for VHDL on Openflow
#51 opened by rodrigomelo9 - 0
- 1
- 2
Feature request: Set TCL filename to project name
#45 opened by gts-bzi - 1
Add a Vivado example to run elaboration
#39 opened by rodrigomelo9 - 0
Add support for OPTIONS
#47 opened by rodrigomelo9 - 2
- 3
Feature request: Make loglevel configurable
#46 opened by gts-bzi - 1
- 3
File paths in TCL on Windows
#41 opened by gts-bzi - 1
Feature request: Option to set VHDL version
#42 opened by gts-bzi - 1
Constraints classification
#40 opened by gts-bzi - 0
Examples to be added
#31 opened by rodrigomelo9 - 0
- 1
Rewrite - Project
#32 opened by rodrigomelo9 - 0
- 1
Lattice support
#30 opened by rodrigomelo9 - 3
Add support for more FOSS programmers
#16 opened by rodrigomelo9 - 1
- 1
- 1
- 0
Improve the Vivado block design example
#14 opened by rodrigomelo9 - 0
- 1
Add support for SymbiFlow
#11 opened by rodrigomelo9 - 0
Add support for Lattice iCEcube2
#7 opened by rodrigomelo9 - 0
Add support for Lattice Radiant
#6 opened by rodrigomelo9 - 0
Add support for Lattice Diamond
#5 opened by rodrigomelo9 - 1
- 1
Doc the current helpers
#24 opened by rodrigomelo9 - 1
Improve/update the docs
#13 opened by rodrigomelo9 - 1
Add set_arch for VHDL
#10 opened by rodrigomelo9 - 1
Add set_define for Verilog
#9 opened by rodrigomelo9 - 2
- 1
Verify set_param (type vs tool)
#8 opened by rodrigomelo9 - 1
- 0
Add support for openFPGALoader
#26 opened by rodrigomelo9 - 4
Load FPGA remote
#25 opened by qarlosalberto