rodrigomelo9
Digital Electronic Engineer. Interested in projects that involve FPGA devices and/or GNU/Linux.
indie SemiconductorBs As, Argentina
Pinned Repositories
FOSS-for-FPGAs
A getting started presentation (with examples) about how to use FLOSS for FPGA development.
rodrigomelo9
My personal repository
verifying-foss-hdl-synthesizers
a project to check the FOSS synthesizers against vendors EDA tools
vhdl2verilog
VHDL93 to Verilog2001 translator
vivado-notes
Notes about how to perform uncommon things with Vivado
xilinx-data-center-recipes
Recipes about how to work with Alveo and AWS EC2 F1
zynq-examples
General-purpose examples based on Zynq (7000, UltraScale+) devices from Xilinx
zynq-petalinux
Zynq (ZCU102, Zynq US+) Petalinux Example
zynq-pl-ps
PL-PS data exchange in Zynq devices
rodrigomelo9's Repositories
rodrigomelo9/FOSS-for-FPGAs
A getting started presentation (with examples) about how to use FLOSS for FPGA development.
rodrigomelo9/vivado-notes
Notes about how to perform uncommon things with Vivado
rodrigomelo9/zynq-pl-ps
PL-PS data exchange in Zynq devices
rodrigomelo9/zynq-examples
General-purpose examples based on Zynq (7000, UltraScale+) devices from Xilinx
rodrigomelo9/zynq-petalinux
Zynq (ZCU102, Zynq US+) Petalinux Example
rodrigomelo9/rodrigomelo9
My personal repository
rodrigomelo9/amba
A presentation about Advanced Microcontroller Bus Architecture
rodrigomelo9/digital-design
rodrigomelo9/docker
Scripts to build and use docker images including GHDL
rodrigomelo9/awesome
A curated list of awesome resources for HDL design and verification
rodrigomelo9/btd
A multi-version Sphinx building tool, based on docker images and shell scripts
rodrigomelo9/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
rodrigomelo9/constraints
Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
rodrigomelo9/containers
Building and deploying container images for open source electronic design automation (EDA)
rodrigomelo9/corescore
CoreScore
rodrigomelo9/ghdl
VHDL 2008/93/87 simulator
rodrigomelo9/ghdl-yosys-plugin
VHDL synthesis (based on ghdl)
rodrigomelo9/hyperledger-recipes
rodrigomelo9/min_night
An easy on the eyes Hugo blog theme with dark mode.
rodrigomelo9/optimuslogic
profile repo
rodrigomelo9/reveal-md
reveal.js on steroids! Get beautiful reveal.js presentations from any Markdown file
rodrigomelo9/symbiflow-examples
Example designs showing different ways to use SymbiFlow toolchains.
rodrigomelo9/tdd-intro
Example of Test Driven Design with VUnit
rodrigomelo9/Termux-packages
Electronic design automation (EDA) package recipes for Termux (Android)
rodrigomelo9/uvm-python
UVM 1.2 port to Python
rodrigomelo9/vboard
Virtual development board for HDL design
rodrigomelo9/vhdl-cfg
Playground to explore and compare how configuration is handled by different tools for development of VHDL projects
rodrigomelo9/vivado-sta
rodrigomelo9/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
rodrigomelo9/wavedrom
:ocean: Digital timing diagram rendering engine