olofk/edalize

Issues

• Unsupported Spyglass design constraints file (`.sgdc` files)

  #448 opened a month ago by amal-araweelo
  1

• The Riviera pro backend of Edalize has minimal VHDL functionality

  #446 opened a month ago by GCHQDeveloper211
  0

• Outdated Spyglass Backend (missing fields)

  #444 opened 2 months ago by amal-araweelo
  0

• Not possible to add variables to Makefile with flow API

  #443 opened 2 months ago by nicorum
  0

• flow_options are not checked

  #441 opened 3 months ago by olofk
  0

• Reporting module test reports issues with numpy.dsize

  #440 opened 3 months ago by olofk
  0

• Symbiflow tool doesn't pass Yosys parameters when using VPR as PnR

  #434 opened 6 months ago by carlosedp
  1

• Edatool.tool_options.get() returns string "None" rather than NoneType

  #436 opened 5 months ago by shareefj
  0

• edalize/flows/edaflow.py # Yeah, I know. It's just a temporary hack

  #431 opened 7 months ago by rivos-pgr
  1

• Error using f4pga flow for Xilinx

  #435 opened 5 months ago by carlosedp
  0

• Passing Verilog string parameters with quotes

  #430 opened 7 months ago by meiniKi
  0

• Jinja2 issue witth edarool loader

  #419 opened 8 months ago by CCCDDDEEEFFF
  4

• Not possible to fully suppress stdout in edatool API?

  #428 opened 7 months ago by keegandent
  0

• How to read an EDIF netlist into Vivado that isn't the toplevel?

  #426 opened 7 months ago by shareefj
  0

• Incorrect toplevel name used when loading EDIF netlist in Vivado

  #425 opened 7 months ago by shareefj
  0

• Yosys: `configure_main` should check for "file_type" in fileset, or provide a default

  #424 opened 7 months ago by Isweet
  0

• Vivado flow not re-run when Verilog parameter is changed

  #423 opened 8 months ago by keegandent
  3

• QSys Pro 23 files are not processed correctly by the filter

  #417 opened 8 months ago by GCHQDeveloper137
  4

• Add update_compile_order to vivado workflow

  #416 opened 9 months ago by andriami
  1

• `make_libraries_directories` on Windows fails due to `mkdir -p`

  #403 opened a year ago by pintert3
  3

• Vars do not survive Edaflow

  #415 opened 10 months ago by psi-chuffine
  0

• GHDL Support for cocotb simulation flow

  #411 opened 10 months ago by psi-chuffine
  2

• Testsuite fails intermittently

  #368 opened 2 years ago by yurivict
  6

• Simulating Vivado IPs (xci, bd)

  #399 opened a year ago by adrianmrd
  4

• explicit dependencies for vunit

  #350 opened a year ago by nopeslide
  0

• ImportError: cannot import name 'get_edatool' from 'edalize' (unknown location)

  #379 opened 2 years ago by rafaelnp
  4

• Efinix FPGA support

  #378 opened a year ago by sebinho
  8

• Support a Vivado IP-packaging flow

  #393 opened a year ago by McSherry
  2

• Modelsim missing in tools

  #388 opened a year ago by garankonic
  0

• filelist.py uses python 3.8 syntax

  #374 opened 2 years ago by dbesse
  5

• How best to fix filelist backend

  #372 opened 2 years ago by shareefj
  3

• Xcelium: file list

  #381 opened 2 years ago by pantikov
  1

• Why is the user guide html that I generated empty.

  #376 opened 2 years ago by salmansheikh
  3

• vivado xsim support for xci or xilinx ip

  #344 opened 2 years ago by skokvermon
  5

• Skipping bitstream generation in vivado

  #370 opened 2 years ago by javValverde
  8

• support for include file in yosys

  #361 opened 2 years ago by bat52
  2

• gnu make on windows 10

  #352 opened 2 years ago by bolzal
  1

• Disabling yosys's synthesis

  #365 opened 2 years ago by Henkru
  1

• F4PGA/Symbiflow Backend

  #323 opened 2 years ago by Pocketkid2
  12

• yosys: wrong target name in Makefile, if output_name tool option is used

  #363 opened 2 years ago by Henkru
  0

• Support for Questasim

  #356 opened 2 years ago by hossein1387
  1

• quartus qsys path seperator on windows 10

  #351 opened 2 years ago by bolzal
  0

• Vivado block design support is broken

  #349 opened 2 years ago by shareefj
  0

• PNR key-value pair gets lost when running vivado

  #334 opened 2 years ago by GCHQDeveloper211
  1

• usage of packages and tool classes

  #340 opened 2 years ago by csquaredphd
  1

• EDAM file: toplevel list of string

  #343 opened 2 years ago by qarlosalberto
  1

• Ip cores provide to bd file in Vivado did not add to project and updated.

  #339 opened 2 years ago by Readon
  0

• Yosys, arch=xilinx fails because of syntax error in write_blif command

  #320 opened 2 years ago by armleo
  1

• Vivado method missing for programming FPGA (with fusesoc)

  #317 opened 2 years ago by patrickerich
  6

• vopt_options missing in modelsim.py

  #315 opened 3 years ago by oholimoli
  4