Pinned Repositories
FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
FazyRV-ExoTiny
flexbex
logIP
Logic Analyzer IP Core
Nokia_5110_Design_Clock
[WIP] A little project using a Nokia 5110 display and an Arduino Nano + DS3231 RTC to build a neat clock.
RV32I_SC_Logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
SimIO
SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.
smsbox
This fun project receives text messages (sms) and prints them via the thermal printer
tt03-another-piece-of-pi
Tiny Tapeout 03: Another Piece of Pi
tt06-FazyRV-ExoTiny
meiniKi's Repositories
meiniKi/FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
meiniKi/logIP
Logic Analyzer IP Core
meiniKi/SimIO
SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.
meiniKi/flexbex
meiniKi/RV32I_SC_Logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
meiniKi/FazyRV-ExoTiny
meiniKi/tt03-another-piece-of-pi
Tiny Tapeout 03: Another Piece of Pi
meiniKi/tt06-FazyRV-ExoTiny
meiniKi/apicula
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
meiniKi/atmega-xmega-soft-core
Mega/Xmega soft core RTL design.
meiniKi/blog_yosyshq
meiniKi/edalize
An abstraction library for interfacing EDA tools
meiniKi/embench-iot
The main Embench repository
meiniKi/embench-tester
meiniKi/esr31web
meiniKi/KostalPikoPy
A package for working with a Piko Inverter from Kostal
meiniKi/litex
Build your hardware, easily!
meiniKi/MAX7219_dotMatrixDisplay
an c++ Arduino library to drive a string of MAX7219 dot matrix displays
meiniKi/clash-ethernet
A fully configurable Ethernet core written in Clash.
meiniKi/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
meiniKi/JSON.sv
SystemVerilog package for reading, manipulating, and writing JSON-formatted data
meiniKi/nextpnr
nextpnr portable FPGA place and route tool
meiniKi/nextpnr-tests
meiniKi/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
meiniKi/qerv
meiniKi/sock.sv
A simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection.
meiniKi/Streamliner
meiniKi/tinybricks
Bootsector bricks game
meiniKi/tt05-submission-template
Submission template for Tiny Tapeout 05
meiniKi/vcd
VCD file (Value Change Dump) command line viewer