verilator
There are 143 repositories under verilator topic.
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
ultraembedded/cores
Various HDL (Verilog) IP Cores
olofk/edalize
An abstraction library for interfacing EDA tools
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
ZipCPU/wbuart32
A simple, basic, formally verified UART controller
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
ZipCPU/dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
ZipCPU/autofpga
A utility for Composing FPGA designs from Peripherals
ZipCPU/vgasim
A Video display simulator
ZipCPU/openarty
An Open Source configuration of the Arty platform
ZipCPU/dpll
A collection of phase locked loop (PLL) related projects
ZipCPU/wbscope
A wishbone controlled scope for FPGA's
dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
IBM/hdl-tools
Facilitates building open source tools for working with hardware description languages (HDLs)
ZipCPU/interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
FDUCSLG/ICS-2021Spring-FDU
Introduction to Computer Systems (II), Spring 2021
tymonx/virtio
Virtio implementation in SystemVerilog
ZipCPU/wbi2c
Wishbone controlled I2C controllers
ben-marshall/croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
sgherbst/svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
ZipCPU/zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
vmunoz82/eda_tools
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
fredrequin/verilator_xilinx
Re-coded Xilinx primitives for Verilator use
dbhi/vboard
Virtual development board for HDL design
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
ZipCPU/dbgbus
A collection of debugging busses developed and presented at zipcpu.com
ZipCPU/s6soc
CMod-S6 SoC
microdynamics-cpu/tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2