verilator

There are 159 repositories under verilator topic.

  • verilator

    verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    Language:C++3.1k724k702

  • ultraembedded/riscv

    RISC-V CPU Core (RV32IM)

    Language:Verilog1.5k5319265

  • ZipCPU/zipcpu

    A small, light weight, RISC CPU soft core

    Language:Verilog1.5k6328173

  • ultraembedded/biriscv

    32-bit Superscalar RISC-V CPU

    Language:Verilog1.1k3225187

  • chipsalliance/Cores-VeeR-EH1

    VeeR EH1 core

    Language:SystemVerilog89657103232

  • ultraembedded/cores

    Various HDL (Verilog) IP Cores

    Language:Verilog833495224

  • olofk/edalize

    An abstraction library for interfacing EDA tools

    Language:Python71333175213

  • dpretet/async_fifo

    A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

    Language:Verilog37812690

  • mshr-h/vscode-verilog-hdl-support

    HDL support for VS Code

    Language:TypeScript3361222182

  • ZipCPU/sdspi

    SD-Card controller, using either SPI, SDIO, or eMMC interfaces

    Language:Verilog311121648

  • ZipCPU/wbuart32

    A simple, basic, formally verified UART controller

    Language:Verilog31015350

  • chipsalliance/Cores-VeeR-EL2

    VeeR EL2 Core

    Language:SystemVerilog298268389

  • tymonx/logic

    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

    Language:SystemVerilog28131160

  • ZipCPU/dblclockfft

    A configurable C++ generator of pipelined Verilog FFT cores

    Language:C++245131340

  • ZipCPU/autofpga

    A utility for Composing FPGA designs from Peripherals

    Language:C++18417522

  • ZipCPU/vgasim

    A Video display simulator

    Language:Verilog17314722

  • ZipCPU/openarty

    An Open Source configuration of the Arty platform

    Language:Verilog13214424

  • ZipCPU/dpll

    A collection of phase locked loop (PLL) related projects

    Language:Verilog1089127

  • chili-chips-ba/wireguard-fpga

    Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

    Language:Verilog1079130
  • HaDes-V

    tscheipel/HaDes-V

    HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

    Language:SystemVerilog86427

  • ZipCPU/wbscope

    A wishbone controlled scope for FPGA's

    Language:Verilog83816

  • dpretet/svut

    SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

    Language:Python8031617

  • ethanuppal/marlin

    🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

    Language:Rust6313012

  • IBM/hdl-tools

    Facilitates building open source tools for working with hardware description languages (HDLs)

    Language:Perl6313212

  • ZipCPU/interpolation

    Digital Interpolation Techniques Applied to Digital Signal Processing

    Language:Verilog634113

  • ZipCPU/wbi2c

    Wishbone controlled I2C controllers

    Language:Verilog526012

  • FDUCSLG/ICS-2021Spring-FDU

    Introduction to Computer Systems (II), Spring 2021

    Language:C++502017

  • sgherbst/svreal

    Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

    Language:SystemVerilog47679

  • tymonx/virtio

    Virtio implementation in SystemVerilog

    Language:SystemVerilog474111

  • ben-marshall/croyde-riscv

    A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

    Language:SystemVerilog46237

  • fredrequin/verilator_xilinx

    Re-coded Xilinx primitives for Verilator use

    Language:Verilog45314

  • vmunoz82/eda_tools

    A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.

    Language:Dockerfile45226

  • ZipCPU/zbasic

    A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

    Language:Verilog433107

  • dbhi/vboard

    Virtual development board for HDL design

    Language:VHDL42507

  • ZipCPU/dbgbus

    A collection of debugging busses developed and presented at zipcpu.com

    Language:Verilog41617

  • ZipCPU/s6soc

    CMod-S6 SoC

    Language:Verilog40915