Issues
- 2
Request to review Lint Issues in Veer RTL
#166 opened by amullick007 - 7
Error while build through "make irun"
#164 opened by ajaysilla - 0
EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?
#169 opened by xiaolei-cheng - 1
CDC Error
#160 opened by Syed-mudabbir-ahsan - 0
- 0
FuseSoC core description file is missing
#165 opened by olofk - 0
Synthesis issue due to perr_dat_ff signal
#149 opened by calebofearth - 6
Does not build
#133 opened by algrobman - 3
Compilation fails
#134 opened by algrobman - 2
SRAM instance export
#145 opened by calebofearth - 2
Caliptra JTAG TdoEn missing output
#159 opened by nstewart-amd - 11
- 0
Does this design work with VCS/Cadence/Mentor simulators after memories were moved from design to tb_top?
#163 opened by algrobman - 0
- 0
UCR in synthesis
#158 opened by Syed-mudabbir-ahsan - 2
Swerv RISC V
#137 opened by navroops17 - 4
- 0
- 0
- 6
- 5
- 0
Add support for DMI export to system
#148 opened by calebofearth - 1
compile fail with TEST=dhry
#136 opened by hbhbts - 2
Make failed, `Unavailable multilib`
#132 opened by wplf - 1
Issue with dhry test
#107 opened by cartersmith15 - 0
Two State Logic LINT violations - el2_pdef.vh
#105 opened by nstewart-amd - 0
WFI instruction is missing?
#104 opened by Risto97 - 1
Replacing hand instantiated synchronizer flops
#103 opened by nstewart-amd - 9
Replacing hand instantiated clock gate cells
#50 opened by rahuljainNV - 7
Synthesis dc_shell giving error while reading: parameter el2_param_t pt = '{
#46 opened by rahulsharmab - 5
RV_ASSERT_ON is always enabled
#58 opened by nstewart-amd - 3
- 0
RISC-V COMPLIANCE RUNNING ON SweRV El2
#45 opened by KinzaQamar - 1
DCCM Region 0x0008_0000
#44 opened by KinzaQamar - 1
rvdffppe elab issue
#73 opened by howardtr - 3
srai srli opcode swap in SweRV
#42 opened by RehanEjaz - 6
DFT overrides after any logic on resets
#52 opened by rahuljainNV - 12
Hiding assertions code from design tools
#49 opened by rahuljainNV - 0
VeeR defines uniquification
#59 opened by nstewart-amd - 0
- 2
- 3
RISC-V compliance on EL2
#43 opened by KinzaQamar - 1
Error: unrecognized opcode csrw
#41 opened by kuoyaoming93 - 0
branch prediction understanding
#40 opened by KinzaQamar - 6
display statement in el2_ifu.sv
#39 opened by KinzaQamar - 8
Machine Timer Interrupt
#38 opened by HamzaShabbir517 - 0
understanding Branch Prediction
#37 opened by KinzaQamar - 5
How to fix load region prediction error
#36 opened by wenjiegong - 21
PIC Configuration
#35 opened by HamzaShabbir517 - 2
Internal timer interrupt service routine
#34 opened by RehanEjaz