axi4
There are 53 repositories under axi4 topic.
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
Hanley-Yao/Zynq7010_eink_controller
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
taichi-ishitani/tvip-axi
AMBA AXI VIP
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
aignacio/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
WangXuan95/FPGA-DDR-SDRAM
An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
OSVVM/AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
loykylewong/FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
ultraembedded/core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
mmxsrup/axi4-interface
AXI4 and AXI4-Lite interface definitions
ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
ultraembedded/core_dvi_framebuffer
Minimal DVI / HDMI Framebuffer
ultraembedded/core_dbg_bridge
UART -> AXI Bridge
airhdl/spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
ultraembedded/core_spiflash
SPI-Flash XIP Interface (Verilog)
ic-lab-duth/NoCpad
HLS for Networks-on-Chip
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
ultraembedded/core_ftdi_bridge
FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
dpretet/friscv
RISCV CPU implementation in SystemVerilog
ultraembedded/cortex_m0_wrapper
Cortex-M0 DesignStart Wrapper
oscc-ip/sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
nhynes/chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
dpretet/meduram
Multi-port BRAM IP for ASIC and FPGA
rggen/rggen-sv-rtl
Common SystemVerilog RTL modules for RgGen
yohanes-erwin/zynq7000
[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol
DOUDIU/Hardware-Implementation-of-Video-Stitching
This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
RISMicroDevices/RMM4NC30F2X
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
xunqianxun/liguoqi-rv64-cpu
RISC-V 64 CPU
gednyengs/dma
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
RISMicroDevices/OpenNCB
Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)
rlee287/hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
ShanghaitechGeekPie/chisel3-typed-axi4
A group of typed definition of AXI4 in Chisel3.
signature-ip-ai/amba-tlm
AMBA TLM Library