processor
There are 712 repositories under processor topic.
pdfcpu/pdfcpu
A PDF processor written in Go.
oshi/oshi
Native Operating System and Hardware Information
unifiedjs/unified
☔️ interface for parsing, inspecting, transforming, and serializing content through syntax trees
intel/pcm
Intel® Performance Counter Monitor (Intel® PCM)
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cyring/CoreFreq
CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.
basicmi/AI-Chip
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
SpongePowered/Mixin
Mixin is a trait/mixin and bytecode weaving framework for Java using ASM
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
sp00n/corecycler
Script to test single core stability, e.g. for PBO & Curve Optimizer on AMD Ryzen or overclocking/undervolting on Intel processors
antonblanchard/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
PrincetonUniversity/openpiton
The OpenPiton Platform
takahirox/riscv-rust
RISC-V processor emulator written in Rust+WASM
mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
soyuka/pidusage
Cross-platform process cpu % and memory usage of a PID
howerj/forth-cpu
A Forth CPU and System on a Chip, based on the J1, written in VHDL
zswang/jdists
A feature rich code block preprocessing tool.
Hargne/jest-html-reporter
Jest test results processor for generating a summary in HTML
skordal/potato
A simple RISC-V processor for use in FPGA designs.
diegoulloao/ioquake3-mac-install
install ioquake3 on macOs in one command (apple silicon support)
dkelosky/jest-stare
Jest HTML Reporter and Results Processor
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
a8m/mark
A markdown processor written in Go. built for fun.
sn99/Optimizing-linux
A simple guide for optimizing linux 🐧 in detail
stnolting/neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
AristurtleDev/monogame-aseprite
A Cross Platform C# Library That Adds Support For Aseprite Files in MonoGame Projects.
riscv-steel/riscv-steel
RISC-V 32-bit microcontroller developed in Verilog
stylecow/stylecow
Modern CSS to all browsers
freecableguy/v3x4
Intel(R) Xeon(R) Processor Max Effort Turbo Boost UEFI DXE driver
autopkg/homebysix-recipes
AutoPkg recipes all the way from Seattle, WA.
KASIRGA-KIZIL/tekno-kizil
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
theorchard/monolog-cascade
Configure multiple loggers and handlers in the blink of an eye
GreenWaves-Technologies/gap_sdk
SDK for Greenwaves Technologies' GAP8 IoT Application Processor
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog