asic-design
There are 86 repositories under asic-design topic.
hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
google/qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
stnolting/neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
cpc/openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
AUCOHL/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
thousrm/universal_NPU-CNN_accelerator
hardware design of universal NPU(CNN accelerator) for various convolution neural network
librelane/librelane
ASIC implementation flow infrastructure
KastnerRG/cgra4ml
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
JeffDeCola/my-verilog-examples
A place to keep my synthesizable verilog examples.
lethalbit/kicad-pdk-libs
KiCad symbol library for sky130 and gf180mcu PDKs
dpretet/friscv
RISCV CPU implementation in SystemVerilog
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
shrine-maiden-heavy-industries/torii-hdl
A Python-based HDL and framework for silicon-based witchcraft
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
dpretet/bster
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
kagandikmen/TPU.sv
Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1
arhamhashmi01/rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
sdnellen/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
OrsuVenkataKrishnaiah1235/RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
AhmedAmrAbdellatif/Multi-Clock-Domain-System
Design & Implementation of Multi Clock Domain System using Verilog HDL
AnoushkaTripathi/NASSCOM-VSD-SoC-design-Program
In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)
mostafa-elgendy22/PrUcess
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
rubinsteina13/SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
akira2963753/Low-Cost-AI-Accelerator-Based-on-TPU
This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.
SinaKarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
abdelazeem201/LEON2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
Aperture-Electronic/Blockdiagramm.Avalonia
Blockdiagramm is a graphical block design tool for IC design
electronics-and-drives/SPAM
SKILL Package Manager