asic-design
There are 69 repositories under asic-design topic.
hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
google/qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
stnolting/neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
cpc/openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
AUCOHL/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
thousrm/universal_NPU-CNN_accelerator
hardware design of universal NPU(CNN accelerator) for various convolution neural network
KastnerRG/cgra4ml
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
JeffDeCola/my-verilog-examples
A place to keep my synthesizable verilog examples.
lethalbit/kicad-pdk-libs
KiCad symbol library for sky130 and gf180mcu PDKs
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
dpretet/friscv
RISCV CPU implementation in SystemVerilog
sdnellen/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
dpretet/bster
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
OrsuVenkataKrishnaiah1235/RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
mostafa-elgendy22/PrUcess
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
shrine-maiden-heavy-industries/torii-hdl
A modern hardware definition language and toolchain based on Python
AhmedAmrAbdellatif1/Multi-Clock-Domain-System
Design & Implementation of Multi Clock Domain System using Verilog HDL
arhamhashmi01/rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
electronics-and-drives/SPAM
SKILL Package Manager
rubinsteina13/SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Aperture-Electronic/Blockdiagramm.Avalonia
Blockdiagramm is a graphical block design tool for IC design
SinaKarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
andrsmllr/magic_vlsi_sky130_examples
Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
abdelazeem201/LEON2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
neeraj1397/A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
rubinsteina13/SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
Visruat/VSD-TCL
TCL Script automating the frontend of ASIC design