Pinned Repositories
VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
fusesoc-cores
FuseSoC standard core library
fusesoc-generators
A collection of core generators to use with FuseSoC
corescore
CoreScore
edalize
An abstraction library for interfacing EDA tools
fifo
Generic FIFO implementation with optional FWFT
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
ipyxact
Python-based IP-XACT parser
serv
SERV - The SErial RISC-V CPU
vidbo
Virtual Development Board
olofk's Repositories
olofk/serv
SERV - The SErial RISC-V CPU
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
olofk/edalize
An abstraction library for interfacing EDA tools
olofk/corescore
CoreScore
olofk/ipyxact
Python-based IP-XACT parser
olofk/subservient
Small SERV-based SoC primarily for OpenMPW tapeout
olofk/wb_intercon
Wishbone interconnect utilities
olofk/fusesocotb
Quick'n'dirty FuseSoC+cocotb example
olofk/qerv
olofk/underserved
olofk/uart16550
UART 16550 core
olofk/spi_ram_loader
SPI RAM loader
olofk/opentitan
OpenTitan: Open source silicon root of trust
olofk/aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
olofk/common_cells
Common SystemVerilog components
olofk/Cores-VeeR-EH1
SweRV EH1 core
olofk/tt08-vga-drop
"The Drop" ASIC 640x480 60Hz audio visual demo
olofk/axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
olofk/riscv-formal
RISC-V Formal Verification Framework
olofk/riscv-opcodes
RISC-V Opcodes
olofk/apb
APB Logic
olofk/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
olofk/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
olofk/gpio
Parametric GPIO Peripheral
olofk/hossein1387.github.io
Personal Website
olofk/keball
Regardless if you are 13 years old or retired, you might want to run keball
olofk/olofk.github.io
olofk/prince
The Prince lightweight block cipher in Verilog.
olofk/subservient_gfmpw1
https://caravel-user-project.readthedocs.io
olofk/subtest