corescore: A Verilog repository from olofk

Background

CoreScore is an award-giving benchmark for FPGAs and their synthesis/P&R tools. It tests how many SERV cores that can be put into a particular FPGA.

Some more background about CoreScore can be found in the SERV introduction video.

Set up a workspace directory and get the FuseSoC base library

mkdir workspace
cd workspace
fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores

Add CoreScore as a library in your workspace

fusesoc library add corescore https://github.com/olofk/corescore

Check available corescore targets
```
fusesoc core show corescore
```
Build one of the supported targets (cyc1000 is one of the currently supported cores)
```
fusesoc run --target=cyc1000 corescore
```
If the board is connected it will be automatically programmed. Otherwise connect it and run fusesoc run --run --target=cyc1000 corescore to program without rebuilding
Run the corecount utility (Might need to adjust for the correct UART port)
```
python3 fusesoc_libraries/corescore/sw/corecount.py /dev/ttyUSB0
```