/dpll

A collection of phase locked loop (PLL) related projects

Primary LanguageVerilog

I'd like to post about some simple and some basic Phase Locked Loop algorithms. To do this I'm going to need some demo code, which I'll keep in this repository.

Blog posts

I recently posted two articles describing the components of a basic PLL, and hence the implementation found in this repository. These are:

  1. How to build a Numerically Controlled Oscillator (NCO) within an FPGA.

  2. The Logic PLL based upon the code in rtl/sdpll.v.

If the Lord is willing, I may go deeper and describe some other PLL implementations as well--such as the sample time tracking PLL that I recently added.

Tutorial slides

I placed a quick/short set of tutorial slides in the doc/ directory. Feel free to browse them and see what you think.

License

All of the source code in this repository is released under the GPLv3. If these conditions are not sufficient for your needs, other licenses terms may be purchased.