pll
There are 61 repositories under pll topic.
lakshmi-sathi/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
ZipCPU/dpll
A collection of phase locked loop (PLL) related projects
pavelmc/Si5351mcu
Arduino Si5351 library tuned for size and click free.
muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
iDoka/eda-scripts
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
super1207/FOC
sensorless fixed point foc use smo and pll in stm32
muhammadaldacher/Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
r4d10n/iCEstick-hacks
iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
parasgidd/avsdpll_3v3
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
NightIsDark/RFFC
RFFC2071 C8051F330
ilyajob05/verilog_modules
verilog modules
qff233/FOC
FOC driver library written in Rust
sascha-kirch/Bit_Error_Tester
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
XiangYyang/SOGI-PLL
Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop
abranhe/react-pll
<Pll/> React Programming Language Logo Component.
aieask/vsd_pll
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
Enanter/ADPLL
All Digital Phase-Locked Loop
infini8-13/riscv-ms-soc
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
zhinst/blogs
Support files for blog posts of Zurich Instruments
microchip-pic-avr-solutions/mchv3-dspic33ck256mp508-an1206
Sensorless FOC (PLL estimator) of AC induction motor with field weakening
americodias/sca_pll
PLL Simulator in SystemC-AMS
Yongxiang-Guo/ADF4351_PLL
Using ADF4351/PLL to get the frequency you want by STM32F103 !
muhammedkurtulus/sogi-pll-fll-implement
SOGI-PLL/FLL algorithm in C | Nuvoton | Sine Look Up Table
sv1onw/Si5351_OLED_DFS
Very minimalistic 20meter transceiver Digital Frequency Synthesizer with 0.96 or 1.3 inch 128x64 OLED Display for Ham-radio use
Eyantra698Sumanto/VSDOpen_PLL_Tutorial
This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
frifle/adventskalender
Ein alternativer Elektronik-Adventskalender für das Jahr 2023
PU2REO/Si5351ArduinoLite
Library for the Si5351A (10 MSOP - 3 Clocks Only) clock generator IC in the Arduino environment , based on NT7S library.
ranjith-dhananjaya/20GHz-integer-N-PLL-in-65nm-CMOS-process
Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
sv1onw/Si5351_OLED_DFS_CW
Modified version of Si5351_OLED_DFS for simple CW TX use or DC receiver.
merledu/jigsaw
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
oliviercotte/All-digital-modulator
All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
tejokrishna10/pll-design-osu-180nm
This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node
FPGAwars/icePLL
PLL collection for IceStudio
lmartorella/lm7001_si470_bridge
LM7001 to Si4703 FM tuner bridge
saiakarsh193/PyCube-Solver
Rubik's cube solver using CFOP
TU-Darmstadt-APQ/MTS_module
Module for AOM-based modulation transfer spectroscopy (MTS) signal generation.