infini8-13/riscv-ms-soc
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
VerilogGPL-3.0
No issues in this repository yet.
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
VerilogGPL-3.0
No issues in this repository yet.