/verilog_modules

verilog modules

Primary LanguageVerilogMIT LicenseMIT

The library is designed to work on the Nexys 4 Artix-7 FPGA Trainer Board from Digilent

verilog modules

  • sender udp
  • receiver udp
  • ethernet ip
  • rmii
  • i2c
  • spi
  • uart
  • usart
  • cyclic timer
  • memory buffer
  • 7-segment indicators
  • synchronization clocks

Example of the program on NEXUS 4 https://youtu.be/khbDWAvb528