modelsim
There are 232 repositories under modelsim topic.
olofk/edalize
An abstraction library for interfacing EDA tools
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
suoto/hdl_checker
Repurposing existing HDL tools to help writing better code
loykylewong/FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
Paebbels/JSON-for-VHDL
A JSON library implemented in VHDL.
prajwalgekkouga/AHB-to-APB-Bridge
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
25th-engineer/HFUT_2020_MIPS_CPU
合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。
RomeoMe5/DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
MJoergen/HyperRAM
Portable HyperRAM controller
suoto/vim-hdl
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
arthurmteodoro/install-quartus-linux
Tutorial de instalação do Quartus Prime no Linux
ItzzInfinity/100-days-of-RTL
Trying to get a new skill
tianrenz2/Single-Cycle-Processor
Single-Cycle RISC-V Processor in systemverylog
MaorAssayag/Architecture-of-CPU-projects
VHDL , ModelSIM, Quartus, FPGA, Image Processing
Amirarsalan-sn/RISCV-multi-cycle-processor
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
baleinesurseine/macOsQuartus
Dockerize altera's Quartus ii software and run it on macOS
esynr3z/pyhdlsim
Example of Python and PyTest powered workflow for a HDL simulation
kimianoorbakhsh/Verilog-Matrix-Multiplier
Final Project for Digital Systems Design Course, Fall 2020
NikLeberg/cosim_jtag
Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.
htminuslab/Modelsim-Unicorn
Modelsim QEMU Unicorn integration via the FLI
cclienti/wavedisp
Python classes to create agnostic wave files for HDL simulator viewer
DylanVanAssche/digitale-synthese
DSSS Wireless transmit-receive system in VHDL
LamaNIkesh/MScFPGAStuff
My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA
Moodrammer/PDP-11
:computer: Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor
tharinduSamare/Multicore_processor_verilog_design
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
kdurant/uvm_study
study uvm step by step
MJoergen/Avalon
Utilities for Avalon Memory Map
MUDAL/Altera_FPGA_Projects
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
SinaKarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
SACHINUR17/VLSI-Design-Verification-Projects
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
Paebbels/pyIPCMI
A Python-based IP Core Management Infrastructure.
Shahriar-0/Computer-Architecture-Course-Projects-S2023
Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline
theSergeyGusev/svReadWrite_pcap
simple read/write pcap tasks for SystemVerilog test
Choaib-ELMADI/getting-started-with-systemverilog
Getting started with SystemVerilog: Hardware Description Language for design and verification.