DylanVanAssche/digitale-synthese

Issues

• Hardware details for porting

  #44 opened 4 years ago by hyanki
  17

• Global hardware test on Virtex II Pro

  #10 opened 7 years ago by DylanVanAssche
  2

• Preamble and data are confused when counter value > 0

  #42 opened 7 years ago by DylanVanAssche
  1

• Build hardware file

  #9 opened 7 years ago by DylanVanAssche
  1

• Total testbench

  #39 opened 7 years ago by DylanVanAssche
  1

• Receiver Top File

  #28 opened 7 years ago by DylanVanAssche
  0

• Access Layer

  #27 opened 7 years ago by DylanVanAssche
  0

• Application layer file corrupted

  #35 opened 7 years ago by DylanVanAssche
  0

• Datalatch file corrupt

  #33 opened 7 years ago by DylanVanAssche
  0

• Datalink shiftreg corrupt

  #31 opened 7 years ago by DylanVanAssche
  0

• DPLL

  #17 opened 7 years ago by DylanVanAssche
  0

• Clean up code for more consistency

  #29 opened 7 years ago by DylanVanAssche
  0

• PN generator + bit NCO

  #19 opened 7 years ago by DylanVanAssche
  0

• Matched Filter

  #18 opened 7 years ago by DylanVanAssche
  0

• 7 segment decoder

  #14 opened 7 years ago by DylanVanAssche
  0

• Data Latch

  #15 opened 7 years ago by DylanVanAssche
  0

• Corrrelator

  #16 opened 7 years ago by DylanVanAssche
  0

• Data shiftregister

  #20 opened 7 years ago by DylanVanAssche
  0

• Lab notes

  #21 opened 7 years ago by DylanVanAssche
  0

• Fix formatting & typos

  #12 opened 7 years ago by DylanVanAssche
  0

• Dataregister

  #4 opened 7 years ago by DylanVanAssche
  0

• Merge layers into sender

  #8 opened 7 years ago by DylanVanAssche
  0

• Sequence Controller

  #3 opened 7 years ago by DylanVanAssche
  0

• PN generator

  #5 opened 7 years ago by DylanVanAssche
  1

• Multiplexer

  #6 opened 7 years ago by DylanVanAssche
  1

• Edge detector

  #2 opened 7 years ago by DylanVanAssche
  0

• Up-Down counter

  #1 opened 7 years ago by DylanVanAssche
  0