Pinned Repositories
SpireMiniEngine
Development of this project is continued at https://github.com/spire-engine/spire-engine. This repo is no longer updated.
argparse-subcommand-template
betelgeuse
config
digital-design
latte
shale
hofstee's Repositories
hofstee/config
hofstee/digital-design
hofstee/shale
hofstee/latte
hofstee/argparse-subcommand-template
hofstee/betelgeuse
hofstee/atrbvh
Implementation for "Bounding Volume Hierarchy Optimization through Agglomerative Treelet Restructuring"
hofstee/cocotb
Coroutine Co-simulation Test Bench
hofstee/coreir
hofstee/cs448m.github.io
course website for cs448m
hofstee/emb
hofstee/hdl-zoo
hofstee/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4
hofstee/hello-emscripten
hofstee/hello-grpc
hofstee/hippie
hofstee/hofstee.github.io
hofstee/imgui
Dear ImGui: Bloat-free Immediate Mode Graphical User interface for C++ with minimal dependencies
hofstee/lua-verilog
Lua scripts related to Verilog.
hofstee/mflowgen
mflowgen -- A Modular ASIC/FPGA Flow Generator
hofstee/motion-canvas
Visualize Complex Ideas Programmatically
hofstee/NTrace
GPU ray tracing framework.
hofstee/optical-flow
hofstee/playnote-studio
An unofficial Flipnote Studio animation player for the Playdate console!
hofstee/ploc
Parallel Locally-Ordered Clustering for Bounding Volume Hierarchy Construction
hofstee/Prusa-Firmware
Firmware for Original Prusa i3 3D printer by PrusaResearch
hofstee/SpireMiniEngine
hofstee/tmk_keyboard
Keyboard firmwares for Atmel AVR and Cortex-M
hofstee/verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
hofstee/yosys
Yosys Open SYnthesis Suite