amaranth-lang/amaranth

Issues

• Allow comparison of data.View with a dict

  #1414 opened 4 days ago by whitequark
  0

• Add a way to have fine grained control over `oe` for `io.Buffer`, `io.FFBuffer`, `io.DDRBuffer`

  #1416 opened 4 days ago by whitequark
  0

• Enumeration values don't work when used in a constant initializer

  #1413 opened 4 days ago by whitequark
  0

• Views with an array layout should be indexable with a slice

  #1405 opened 8 days ago by whitequark
  1

• `create_missing_domain` uses `platform.request()` in deprecated mode in all platforms

  #1402 opened 8 days ago by whitequark
  0

• `stream.Signature` should allow setting the init value for the payload

  #1404 opened 8 days ago by whitequark
  2

• Add a `PortLike` that can be used in simulation to test designs which instantiate I/O buffers

  #1417 opened 4 days ago by whitequark
  0

• Warn after simulation ends if a domain's clock isn't driven by either logic or testbench

  #1415 opened 4 days ago by whitequark
  0

• VCD files do not display glitches and can get extremely confusing

  #1412 opened 6 days ago by whitequark
  2

• Views with an array layout should have `len()` applicable to them

  #1403 opened 7 days ago by whitequark
  0

• Tracking issue for RFC 36: Async testbench functions

  #1213 opened 3 months ago by zyp
  3

• Tracking issue for RFC 59: Get rid of upwards propagation of clock domains

  #1242 opened 3 months ago by wanda-phi
  0

• Do something with `Value.implies`

  #1239 opened 10 days ago by whitequark
  2

• Tracking issue for RFC 63: Remove `amaranth.lib.coding`

  #1292 opened 10 days ago by wanda-phi
  0

• Tracking issue for RFC 61: Minimal stream interface

  #1244 opened 10 days ago by whitequark
  0

• Roadmap to Amaranth 0.5

  #1225 opened 10 days ago by whitequark
  1

• Constraint generation from platform resource with `DiffPairs` of type LVDS incorrect.

  #1365 opened 10 days ago by lethalbit
  1

• `AttributeError` caused by `UnusedElaboratable` after an elaboratable has failed its initialization

  #1382 opened 11 days ago by jfng
  1

• Adding simulator processes after starting the simulation is not well-defined

  #1368 opened 15 days ago by whitequark
  2

• Indexing into signals with layouts could be improved

  #1375 opened 15 days ago by isabelburgos
  1

• Zero-length submodule name breaks things

  #1209 opened 15 days ago by tpwrules
  4

• Pyright errors on `m.[If/Elif/Else]`: No `__enter__` or `__exit__`

  #1324 opened 15 days ago by turtlebasket
  1

• Tracking issue for RFC 55: New `lib.io` components

  #1210 opened 3 months ago by wanda-phi
  0

• Pysim should reject async generators

  #1363 opened a month ago by cr1901
  0

• Extremely slow Verilog generation

  #1361 opened a month ago by resistor
  5

• Make `Module` explode if you try to modify it after it's elaborated

  #1350 opened a month ago by whitequark
  0

• Tracking issue for RFC 56: Asymmetric memory port width

  #1211 opened 3 months ago by wanda-phi
  0

• Add `AMDPlatform`, aliasing `XilinxPlatform`

  #1349 opened 2 months ago by whitequark
  0

• Can't emit Verilog/RTLIL with Signature array members

  #1339 opened 2 months ago by eigenform
  1

• Question: Combinational vs Combinatorial

  #1301 opened 2 months ago by X-Illuminati
  7

• Unclear error message on `m.domains.cd_tx = ClockDomain()`

  #1331 opened 2 months ago by whitequark
  0

• Fix failing uploads to TestPyPI from CI

  #1229 opened 2 months ago by whitequark
  1

• Tracking issue for RFC 65: Special formatting for structures and enums

  #1293 opened 2 months ago by wanda-phi
  0

• pysim LHS compiler miscompiles `Slice` of `SwitchValue`

  #1269 opened 2 months ago by wanda-phi
  0

• `Signal.like` is not fully functional with `ShapeCastable`-based signals

  #1285 opened 2 months ago by wanda-phi
  0

• `execute_local_docker()` does not forward SIGINT/ctrl+c to docker subprocess

  #1246 opened 2 months ago by polymerizedsage
  4

• Tracking issue for RFC 62: The `MemoryData` class.

  #1241 opened 2 months ago by wanda-phi
  1

• Tracking issue for RFC 58: Core support for `ValueCastable` formatting

  #1243 opened 3 months ago by wanda-phi
  0

• doc: Reduction operators: .any() vs .bool()

  #1219 opened 3 months ago by meithecatte
  5

• Question: reset-less signals in interfaces

  #1220 opened 3 months ago by daniestevez
  16

• Detect and warn about elaboratables added more than once into the hierarchy

  #1194 opened 3 months ago by wanda-phi
  0

• Wrong verilog for combinatorial module

  #1260 opened 3 months ago by FatsieFS
  2

• verilog output error: syntax error in left side of continuous assignment.

  #1254 opened 3 months ago by alexian79
  2

• Bit width of `Signal(range(1))`

  #1253 opened 3 months ago by tilk
  2

• Signals with private names

  #1223 opened 3 months ago by whitequark
  4

• Add `MemoryData`; like `Signal` but for memories

  #1221 opened 3 months ago by whitequark
  2

• Tracking issue for RFC 54: Initial and reset values on memory read ports

  #1212 opened 3 months ago by wanda-phi
  1

• Kill `Value._lhs_signals` and `Value._rhs_signals`

  #1222 opened 3 months ago by whitequark
  0

• Make the use of `Elaboratable` for elaboratable objects required

  #1216 opened 3 months ago by whitequark
  0

• Tracking issue for RFC 53: Low-level I/O primitives

  #1195 opened 3 months ago by wanda-phi
  0