WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
BluespecGPL-3.0
Issues
- 1
13.1 SPIFlash 读写器
#29 opened by zhouyecs - 0
bsvbuild.sh 链接.c文件的一些问题。
#28 opened by xuzhengli666 - 0
仿真运行失败
#27 opened by androny1012 - 11
bluespec比chisel有优势吗?
#21 opened by stayforapple - 2
EX stage issues
#24 opened by ferryuei - 0
RV32跳转停顿问题
#23 opened by ferryuei - 1
- 0
typo `Light1` -> `Light`
#16 opened by logicshan - 0
- 0
typo `否侧 -> 否则`. 下一行也有一处
#13 opened by logicshan - 1
- 0
typo "哪`两个`规则的顺序是无所谓的"
#12 opened by logicshan - 0
typo 不能放在同一规则内
#10 opened by logicshan - 0
`x <= y + w1;` 被执行
#11 opened by logicshan - 0
这里的"用通过" 把 "用" 字去掉似乎更通顺一些
#17 opened by logicshan - 1
typo "每个对应文件一个模块" -> "每个文件对应一个模块"?
#19 opened by logicshan - 1
typo (后续5.1节会细讲)-> (后续6.1节会细讲)
#20 opened by chinghua0731 - 1
8.4 节部分利用FIFO队列实现流水线的例子
#9 opened by Tigter - 1
用户定义的模块,其方法可以写调度注解吗
#8 opened by zck15 - 3
bsc官方仓库现已提供编译好的二进制
#5 opened by zephray - 3
询问有关rule和descending_urgency的问题
#7 opened by zchliu - 2
詢問硬體學習相關事務
#3 opened by Steve-deltora - 3
Rv32iCPU 运行时报错
#6 opened by zchliu - 1
发现了文章的一处笔误
#4 opened by zchliu - 1
这里TestWire注释是否为笔误
#2 opened by zephray