hardware-description-language
There are 164 repositories under hardware-description-language topic.
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
drom/awesome-hdl
Hardware Description Languages
JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
cucapra/filament
Fearless hardware design
mit-plv/kami
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
mit-plv/koika
A core language for rule-based hardware design 🦑
SystemRDL/PeakRDL
Control and status register code generator toolchain
asyncvlsi/act
ACT hardware description language and core tools.
pc2/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
cyber-anubis/The-HACK-General-Purpose-Computer
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
mikeroyal/VHDL-Guide
VHDL Guide
JeffDeCola/my-verilog-examples
A place to keep my synthesizable verilog examples.
broccolimicro/loom
design and verification of asynchronous circuits
aofarmakis/Nibbling-bits
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
drom/reqack
🔁 elastic circuit toolchain
GSimas/INE5406
📚Repositório da Disciplina INE5406 - Sistemas Digitais
fayizferosh/yosys-tcl-ui-report
5 Day TCL begginer to advanced training workshop by VSD
chaseruskin/legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
povik/fold
high abstraction synthesis
VitorgsRuffo/Building-The-Hack-Computer
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
gergoerdi/retroclash-lib
Library code for upcoming RetroClash book
tilk/yieldfsm
YieldFSM, a DSL for describing finite state machines in Clash
tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
david-palma/mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
m47812/HDL_Converter
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
SnrNotHere16/RISCVSingleCycleProcessor
A RISC-V Single Cycle Processor which is done in verilog.
Choaib-ELMADI/getting-started-with-verilog
Getting started with Verilog: Hardware Description Language for digital circuits design.
estradjm/Code-Portfolio
Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config
dohun-qml/Verilog-HDL
[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리
m47812/hdl_toolbox
A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.
meiniKi/logIP
Logic Analyzer IP Core
Silicon1602/srdl2sv
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.