m47812/HDL_Converter
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
C#AGPL-3.0
Issues
- 0
signed is removed in conversion
#11 opened by m47812 - 1
- 1
Instantiation name placed wrong
#9 opened by m47812 - 0
- 2
Unsupported Syntax versions for Verilog
#2 opened by m47812 - 1
Problems when using "," in comments
#1 opened by m47812