bluespec-systemverilog
There are 18 repositories under bluespec-systemverilog topic.
WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
Raamakrishnan/bsv-for-vscode
Bluespec System Verilog language extension for Visual Studio Code
mchanphilly/vscode-bsv
Bluespec SystemVerilog extension for VS Code
thotypous/sublime-bsv
Bluespec SystemVerilog Package for Sublime Text
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
pbing/J1_BSV
Forth CPU J1 in Bluespec SystemVerilog (BSV)
JoyenBenitto/Quark
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
HYwooo/Docker-BSV-WSL2
🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。
ssk1328/noc_mesh
Bluespec implementation of PG routing algorithm on a network on chip running a SMIPS
DevJPM/BSV-Stuff
To toy around with Bluespec-SystemVerilog and my Basys3 board
johnmaxrin/AF754
A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance
MarcosFagli/Redes_ImplementacaoTCPServer
Implementação do protocolo TCP para a disciplina de Redes de Computadores da Universidade Federal de São Carlos - UFSCar
xushengj/BluespecSystemVerilog-NotepadPlusPlus
Bluespec System Verilog syntax highlighting for Notepad++
AdityaGovardhan/floating-point-unit
Hardware implementation of floating point unit (IEEE-754 compliant) for RISC-V architecture
JoyenBenitto/Bluespec_noob
Learning bluespec with bunch of tutorials and example codes
pbing/fsm_bsv
FSM coding styles in BSV
pbing/Wishbone_BSV
Wishbone/Bluespec Systemverilog Transactors